Table 2-5. Register Organization Summary - Cirrus Logic EP93 Series User Manual

Arm 9 embedded processor family
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ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User's Guide
2
User
r10
r12
r13(sp)
r14(lr)
r15(pc)
cpsr
User mode in Thumb state limits access to the low registers r0-r7. To access to the high
registers, the ARM Core must first revert to the ARM state. The high registers are:
• r0-r12: General purpose read/write 32-bit registers
• r13 (sp): Stack Pointer
• r14 (lr): Link Register
• r15 (pc): Program Counter
• cpsr: Current Program Status Register containing condition codes and operating modes
2-14

Table 2-5. Register Organization Summary

System
Supervisor
r0
r0
r0
r1
r1
r1
r2
r2
r2
r3
r3
r3
r4
r4
r4
r5
r5
r5
r6
r6
r6
r7
r7
r7
r8
r8
r8
r9
r9
r9
r10
r10
r11
r11
r11
r12
r12
r13
r13_svc
r14
r14_svc
pc
pc
cpsr
cpsr
spsr_svc
Note: Colored areas represent banked registers.
Privileged Modes
Exception Modes
Abort
Undefined
r0
r0
r1
r1
r2
r2
r3
r3
r4
r4
r5
r5
r6
r6
r7
r7
r8
r8
r9
r9
r10
r10
r11
r11
r12
r12
r13_abt
r13_und
r14_abt
r14_und
pc
pc
cpsr
cpsr
spsr_abt
spsr_und
Copyright 2007 Cirrus Logic
IRQ
FIQ
r0
r0
r1
r1
r2
r2
Thumb
r3
r3
state low
r4
r4
registers
r5
r5
r6
r6
r7
r7
r8
r8_fiq
r9
r9_fiq
r10
r10_fiq
Thumb
r11
r11_fiq
state high
r12
r12_fiq
registers
r13_irq
r13_fiq
r14_irq
r14_fiq
pc
pc
cpsr
cpsr
spsr_irq
spsr_fiq
DS785UM1

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