Reset Control; Registers; Table 20-1. Real Time Clock Register Memory Map - Cirrus Logic EP93 Series User Manual

Real Time Clock With Software Trim
EP93xx User's Guide

20.1.2 Reset Control

The RTC block level reset operation is a bit complicated. The reset strategy is for the time-
keeping part of the RTC to survive a system reset, and only be initialized by a power-on reset.
The RTC interrupt enable is cleared by a user reset, so that a time count match (alarm
interrupt) would disable with system reset.
The following register is initialized only by PRSTn: RTCSWComp
20
The following registers are initialized by PRSTn: RTCData, RTCMatch, RTCLoad, and
RTCCtrl.

20.1 Registers

Register Descriptions
RTCData
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
20-4

Table 20-1. Real Time Clock Register Memory Map

Address
0x8092_0000
0x8092_0004
0x8092_0008
0x8092_000C
0x8092_0010
0x8092_0098 "RTCSWComp"
29 28 27 26
13 12 11 10
0x8092_0000 - Read Only
0x0000_0000
RTC Data Register. Contains the 32 bit RTC counter value. This counter is
incremented by the 1 Hz clock output from the RTC Trim module.
RTCDR:
Copyright 2007 Cirrus Logic
Name
"RTCData" RTC Data Register
"RTCMatch" RTC Match Register
"RTCSts" RTC Status/EOI Register
"RTCLoad" RTC Load Register
"RTCCtrl" RTC Control Register
RTC Software Compensation
25 24 23 22
RTCDR
9 8 7 6
RTCDR
Counter value.
Description
21 20 19 18
5 4 3 2
17 16
1 0
DS785UM1