22.2.2.4 GPIOTXCOMPLETE
The transmit GPIOTXCOMPLETE interrupt is asserted when all values written to the
AC97S12Data have been transmitted. It is cleared when any data is written to the
AC97S12Data.
22.2.2.5 SLOT2INT
The receive SLOT2INT interrupt is asserted when the AC97S2Data register has new data
that has not been read. By reading the data in the AC97S2Data register the SLOT2INT
interrupt is cleared.
22.2.2.6 SLOT1TXCOMPLETE
The transmit SLOT1TXCOMPLETE interrupt is asserted when all values written to the
AC97S1Data have been transmitted. It is cleared when any data is written to the
AC97S1Data.
22.2.2.7 SLOT2TXCOMPLETE
The transmit SLOT2TXCOMPLETE interrupt is asserted when all values written to the
AC97S2Data have been transmitted. It is cleared when any data is written to the
AC97S2Data.
22.3 System Loopback Testing
A loopback test mode is available for system testing so that data transmitted on SDATAOUT
can also be received on SDATAIN. Loopback mode is entered when a "1" is written to the
LOOP bit in AC97GCR register. For normal operation the LOOP bit must always be "0",
which is also the default state at reset.
Note: For this test mode to work, an external bit clock will need to be supplied.
22.4 Registers
Address
0x8088_0000
0x8088_0004
0x8088_0008
0x8088_000C
0x8088_0010
0x8088_0014
0x8088_0018
0x8088_001C
0x8088_0020
0x8088_0024
0x8088_0028
0x8088_002C
DS785UM1
Table 22-2. AC'97 Register Memory Map
Type
Name
Read/Write
AC97DR1
Read/Write
AC97RXCR1
Read/Write
AC97TXCR1
Read
AC97SR1
Read
AC97RISR1
Read
AC97ISR1
Read/Write
AC97IE1
-
-
Read/Write
AC97DR2
Read/Write
AC97RXCR2
Read/Write
AC97TXCR2
Read
AC97SR2
Copyright 2007 Cirrus Logic
Description
Data read or written from/to FIFO1
Control register for receive
Control register for transmit
Status register
Raw interrupt status register
Interrupt Status
Interrupt Enable
Reserved
Data read or written from/to FIFO2
Control register for receive
Control register for transmit
Status register
AC'97 Controller
EP93xx User's Guide
22
22-5
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