Cirrus Logic EP93 Series User Manual page 382

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
Bit Descriptions:
9
TXDQBLen
31 30
15 14
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
TXDQCurLen
31 30
15 14
Address:
Chip Reset:
9-80
TDBA:
29 28 27 26
13 12 11 10
0x8001_00B4 - Read/Write
0x0000_0000
Unchanged
Transmit Descriptor Queue Base Length register. The Transmit Descriptor
Queue Base Length defines the actual number of bytes in the transmit
descriptor queue, which thereby sets the maximum number of transmit
descriptors that can be supplied to the MAC at any one time. The length
should be set at initialization time and must define an integral number of
transmit descriptors.
RSVD:
TDBL:
29 28 27 26
13 12 11 10
0x8001_00B6 - Read/Write. Note half word alignment.
0x0000_0000
Copyright 2007 Cirrus Logic
Transmit Descriptor Base Address.
25 24 23 22
RSVD
9 8 7 6
TDBL
Reserved. Unknown During Read.
Transmit Descriptor Base Length.
25 24 23 22
RSVD
9 8 7 6
TDCL
21 20 19 18
5 4 3 2
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
DS785UM1