Cirrus Logic EP93 Series User Manual page 423

MAXCNTx
31 30 29 28
15 14 13 12
Address:
MAXCNT0: Channel Base Address + 0x0020 - Read/Write
MAXCNT1: Channel Base Address + 0x0030 - Read/Write
Definition:
x = "0" or "1". Maximum byte count for the buffer. Represents the double buffer
per channel. Only the low order 16 bits are used. Each MAXCNTx register
must be programmed before it's corresponding BASEx register.
Bit Descriptions:
RSVD:
MAXCNTx:
BASEx
31 30 29 28
15 14 13 12
Address:
BASE0: Channel Base Address + 0x0024 - Read/Write
BASE1: Channel Base Address + 0x0034 - Read/Write
Definition:
Base address for the current and next DMA transfer.
Bit Descriptions:
BASEx:
DS785UM1
27 26 25 24
RSVD
11 10 9 8
MAXCNTx
Reserved. Unknown During Read.
Maximum byte count for the buffer.
27 26 25 24
BASEx
11 10 9 8
BASEx
x = "0" or "1". Base address for the current and next DMA
transfer. Loaded with start address after enabling the DMA
Channel, the latter event required to take the Channel
State machine into the STALL state, the former event
required to enter the ON State.
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
23 22 21 20
7 6 5 4
DMA Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
19 18 17 16
3 2 1 0
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