I 2 S Receiver Channel Overview - Cirrus Logic EP93 Series User Manual

2
The I S transmit and receive channels should be disabled before changes are made to the
control registers. Once the new configuration has been set, the channels can be re-enabled
following the specified start order.
If a channel is enabled while the FIFO is empty, no samples are read from the FIFO. The I
controller will parallel load whatever is currently in the left holding register into the shift
register. Once these contents have been shifted out, the right holding register is then parallel
loaded into the shift register and then shifted out. If this occurs after the I
been reset, these holding registers will contain zero. If the I
after an earlier transmission, the holding registers will contain the last samples that were
copied into them. As before, the I
holding register has been loaded into the shift register. At this point, if the FIFO is still empty,
2
the I S controller will assert the FIFO underflow flag. No attempt is made to read the FIFO by
2
the I S controller and the read pointer stays pointing to location 0. The underflow will update
a status bit in the Global Control Status register, I2SGlSts. (See "Register Descriptions" on
page 448.) To clear the underflow the programmer must write at least one left and right stereo
sample to the FIFO. Disabling the I
The status of each FIFO is reflected in the Global Control Status register. There are 5 bits for
each FIFO in this register that reflect the state of the FIFO. They are as follows:
• Tx0_underflow - Gets set when the I
• Tx0_overflow - Gets set when the programmer attempts to write to the FIFO when it is
full.
• Tx0_fifo_empty - Gets set when there no left and right stereo samples in the FIFO.
• Tx0_fifo_half_empty - Gets set when there are 4 left and right stereo samples or less in
the FIFO.
• Tx0_fifo_full - Gets set when there are 8 left and right stereo samples in the FIFO.
2
21.3 I S Receiver Channel Overview
2
The I S Receiver channel enables audio compression algorithms executing on the ARM
Core to receive stereo information from external CODECS.
2
Each I S RX channel provides a single stereo I
channel can operate in master and slave mode. Data is received from the channel input and
transferred into two registers, the left and right stereo pair. The ARM can then read the data
from the channel. The key features are shown below.
• Three Receive data channels, master or slave mode.
• Supports 16/24/32 bit word lengths.
• Programmable left/right word clock polarity on the serial frame.
• Programmable bit clock polarity.
• Programmable data validity, that is, data valid on the rising/negative edge of the bit
clock.
DS785UM1
2
S controller will attempt to read the FIFO after the right
2
S controller will also clear the underflow.
2
S controller reads the FIFO when it is empty.
2
S compliant input channel. The Receive
Copyright 2007 Cirrus Logic
2
I
EP93xx User's Guide
2
S controller has
2
S controller has been re-enabled
S Controller
2
S
21
21-5