Cirrus Logic EP93 Series User Manual page 228

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
Frame Buffer Memory Configuration Registers
7
VidScrnPage
31 30
RSVD
15 14
Address: 0x8003_0028
Default: 0x0000_0000
Definition: Video Screen Page Register
Bit Descriptions:
VidScrnHPage
31 30
RSVD
15 14
Address: 0x8003_002C
Default: 0x0000_0000
Definition: Video Screen Half Page Register
Bit Descriptions:
7-46
29 28 27 26
13 12 11 10
RSVD:
PAGE:
NA:
29 28 27 26
13 12 11 10
RSVD:
Copyright 2007 Cirrus Logic
25 24 23 22
PAGE
9 8 7 6
PAGE
Reserved - Unknown during read
Video Screen Page Starting SDRAM Address - Read/Write
Corresponds to the word address relative to the beginning
of SDRAM of the upper left corner of the video screen to
be scanned out. The absolute AHB address for the video
screen page is determined by the combination of this bit
field as well as the SDSEL bit held in the
register.
Not Assigned. Will return written value during a read.
25 24 23 22
PAGE
9 8 7 6
PAGE
Reserved - Unknown during read
21 20 19 18
5 4 3 2
"VideoAttribs"
21 20 19 18
5 4 3 2
17 16
1 0
NA
17 16
1 0
NA
DS785UM1