Cirrus Logic EP93 Series User Manual page 429

NFBIntEn:
RSS:
NO_HDSK:
PWSC:
INTERRUPT
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Address:
Channel Base Address + 0x0004 - Read/Write
DS785UM1
Setting this bit to "1" enables the generation of the NFB
interrupt in the DMA_BUF_ON state of the DMA channel
buffer state machine. Setting this bit to zero disables
generation of the NFB Interrupt. Normally when the
channel is enabled, this bit should be 1. However in the
case where the current buffer is the last, then this bit can
be cleared to prevent the generation of an interrupt while
the DMA State machine is in the DMA_BUF_ON state.
Request Source Selection.
00 - External DReq.
01 - Internal SSPRx.
10 - Internal SSPTx.
11 - Internal IDE.
When set, the peripheral doesn't require the regular
handshake protocol. This is optional for external DMAs,
but this bit needs to be set for SSP and IDE operations.
Setting this bit will imply the use of a wait state counter
that will mask hardware requests after each DMA write.
Peripheral Wait States Count. Gives the latency (in HCLK
cycles) needed by the peripheral to de-assert its request
line once the M2M transfer is finished.During this latency
period, the DMA channel will not consider any request.
This wait state count is triggered after each peripheral
width transfer, right after the DMA write phase.In the case
of internal DMA, this means that the count will start when
the DMA has had confirmation from AHB that the write is
accepted and done. In the case of an external DMA that
doesn't use a handshaking protocol, the count will start
when the DMA has received the acknowledge of the write
from the SMC.If the acknowledge from the SMC takes too
long to arrive, the processor can still cancel the counter
stall by writing the CONTROL register.
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RSVD
11 10 9 8
RSVD
Copyright 2007 Cirrus Logic
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DMA Controller
EP93xx User's Guide
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NFBint DONEInt STALLInt
10-35
10