Cirrus Logic EP93 Series User Manual page 501

Step
Write a '1' or '0' to the External Bus Width bit in the
2
appropriate
Write Initialize = '0', MRS = '1', and LCR = '0' to the
3
"GlConfig"
Read from the external SDRAM's Mode register
4 with Row and Bank address = 0x2 or 0x3 (see
SDRAM data sheet)
Write Initialize = '1', MRS = '1', and LCR = '0' to the
5
"GlConfig"
Wait 200 μ s
6
Write Initialize = '1', MRS = '0', and LCR = '0' to the
7
"GlConfig"
8 Write Refcnt = 0xB into the
9 Wait for at least 80 SDCLK cycles
Write the normal operating value to the Refcnt field
10
in the
Write Initialize = '0', MRS = '1', and LCR = '0' to the
11
"GlConfig"
Perform a read from each SDRAM in the
"SDRAMDevCfg[3:0]"
address that is read defines the value that is
written into the Mode register (see SDRAM device
datasheet). The address value is dependent on the
12
configuration of the memory system since the
actual SDRAM address pins are mapped
differently onto the processor's address pins for
16- and 32-bit wide memory systems. (This is the
reason for step 2).
Write parameters corresponding to those
programmed into the SDRAM devices Mode
register into the corresponding fields of the
13
"SDRAMDevCfg[3:0]"
the "SDRAMDevCfg[3:0]"register as appropriate
for the given SDRAM usage.
Write Initialize = '0', MRS = '0', and LCR = '0' to the
14
"GlConfig"
DS785UM1
Table 13-4. General SDRAM Initialization Sequence
Action
"SDRAMDevCfg[3:0]" register
register
register
register
"RefrshTimr"
"RefrshTimr" register
register
space. The value of the
register. Write other fields in
register.
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
Reason
'1' specifies 16-bit memory bus width
'0' specifies 32-bit memory bus width
To allow the Mode register inside the
external SDRAM device to be accessed
0x2 -- Burst Length = 4 (32-bit wide
memory bus)
0x3 -- Burst Length = 8 (16-bit wide
memory bus)
To issue continuous NOP accesses
SDRAM requirement
To issue a Pre-Charge All accesses
To provide a refresh every 10 SDCLK
register
cycles
To provide 8 refresh cycles to all
SDRAMs in "SDRAMDevCfg[3:0]"
space
To establish normal refresh operation
To allow the Mode register inside the
SDRAM device to be accessed
To set up the Mode register inside each
SDRAM device
To initialize the SDRAM controller timing
To start normal operation
EP93xx User's Guide
13
13-5