Cirrus Logic EP93 Series User Manual page 682

2
I S Controller
EP93xx User's Guide
2
I S Configuration and Status Register Descriptions
I2STXClkCfg
31 30
21
15 14
Address:
Default
Definition:
Bit Descriptions:
21-26
29 28 27 26
13 12 11 10
RSVD
0x8082_0000 - Read/Write
0x0000_0000
Transmitter clock configuration register.
RSVD:
i2s_tx_bcr:
i2s_tx_nbcg:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
i2s_tx_bcr
Reserved. Unknown During Read.
Defines the TX bit clock rate.
00 - I2STXClkCfg[4] defines the bit clock generation.
01 - Bit clock rate is fixed at 32x. Word length is ignored.
10 - Bit clock rate is fixed at 64x. Word length is ignored.
11 - Bit clock rate is fixed at 128x. Word length is ignored.
Defines TX not bit clock gating mode.
If I2STXClkCfg[5:6] = 00, this bit defines the bit clock rate,
otherwise ignored.
Bit clock rate = 32x if word length is 16.
Bit clock rate = 64x if word length is 32.
Bit clock rate = 64x if word length is 24.
There is a special case when the word length is 24.
If this bit = 0 and the word length is 24, the last 8 cycles
are gated off in each word.
If this bit = 1 and the word length is 24, the last 8 cycles
are not gated off in each word.
21 20 19 18
5 4 3 2
i2s_tx_nbcg i2s_mstr i2s_trel
17 16
1 0
i2s_tckp i2s_tlrs
DS785UM1