Cirrus Logic EP93 Series User Manual page 544

UART1 With HDLC and Modem Control Signals
EP93xx User's Guide
UART1Ctrl
31 30
15 14
14
Address:
Default:
Definition:
Bit Descriptions:
UART1Flag
31 30
15 14
14-22
29 28 27 26
13 12 11 10
RSVD
0x808C_0014 - Read/Write
0x0000_0000
UART1 Control Register
RSVD:
LBE:
RTIE:
TIE:
RIE:
MSIE:
UARTE:
29 28 27 26
13 12 11 10
RSVD
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
LBE RTIE
Reserved. Unknown During Read.
Loopback Enable. If this bit is set to 1, data sent to TXD is
received on RXD. This bit is cleared to 0 on reset, which
disables the loopback mode.
Receive Timeout Enable. If this bit is set to 1, the receive
timeout interrupt is enabled.
Transmit Interrupt Enable. If this bit is set to 1, the transmit
interrupt is enabled.
Receive Interrupt Enable. If this bit is set to 1, the receive
interrupt is enabled.
Modem Status Interrupt Enable. If this bit is set to 1, the
modem status interrupt is enabled.
UART Enable. If this bit is set to 1, the UART is enabled.
Data transmission and reception occurs for UART signals.
25 24 23 22
RSVD
9 8 7 6
TXFE RXFF
21 20 19 18
5 4 3 2
TIE RIE MSIE RSVD
21 20 19 18
5 4 3 2
TXFF RXFE BUSY DCD
17 16
1 0
UARTE
17 16
1 0
DSR CTS
DS785UM1