Cirrus Logic EP93 Series User Manual page 156

System Controller
EP93xx User's Guide
MIRClkDiv
5
31 30
15 14
MENA ESEL
Address:
Default:
Definition:
Bit Descriptions:
5-30
29 28 27 26
13 12 11 10
PSEL RSVD
0x8093_0088 - Read/Write, Software locked
0x0000_0000
Configures MIR clock for the MIR IrDA. Selects input to MIR clock dividers
from either PLL1 or PLL2, and defines a programmable divide value.
RSVD:
MENA:
ESEL:
PSEL:
PDIV:
MDIV:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
PDIV RSVD
Reserved. Unknown During Read.
Enable MIR_CLK divider.
External clock source select.
0 - Use the external XTALI clock input as the clock source.
1 - Use one of the internal PLLs selected by PSEL as the
clock source.
PLL source select.
1 - Select PLL2 as the clock source.
0 - Select PLL1 as the clock source.
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
MIR_CLK divider value. Forms a divide-by-N of the pre-
divide clock output. MIR_CLK is the source clock divided
by PDIV divided by N.
21 20 19 18
5 4 3 2
MDIV
17 16
1 0
DS785UM1