Cirrus Logic EP93 Series User Manual page 673

Definition:
Transmit Control Register
Bit Descriptions:
RSVD:
TXUFIE:
TXEMPTY_int_level:Transmit empty interrupt level select.
I2STXWrdLen
31 30 29 28
15 14 13 12
Address:
0x8082_0030 - Read/Write
Default:
0x0000_0000
Definition:
Transmit Word Length
Bit Descriptions:
RSVD:
WL:
I2STX0En
31 30 29 28
15 14 13 12
Address:
0x8082_0034 - Read/Write
DS785UM1
Reserved. Unknown During Read.
Transmit interrupt enable. Active high
0 - Generate interrupt when FIFO is half empty.
1 - Generate interrupt when FIFO is empty.
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read.
Transmit Word Length.
00 - 16 bit mode
01 - 24 bit mode
10 - 32 bit mode
27 26 25 24
RSVD
11 10 9 8
RSVD
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
23 22 21 20
7 6 5 4
2
I S Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
WL
19 18 17 16
3 2 1 0
i2s_tx0_EN
21-17
21