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1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
10.Wait for TxAct in BMSts to be set and then write the appropriate number of descriptors
remaining in the queue to TXDEnq.
9
9.3 Registers
9-40
Address
0x8001_0000
0x8001_0004
0x8001_0008
0x8001_0010
0x8001_0014
0x8001_0018
0x8001_0020
0x8001_0024
0x8001_0028
0x8001_002C
0x8001_0030 -
0x8001_0034
0x8001_0038
0x8001_003C
0x8001_0040
0x8001_0044
0x8001_0048
0x8001_004C
0x8001_0050 -
0x8001_0055
0x8001_0050 -
0x8001_0057
0x8001_0060
0x8001_0064
0x8001_0068
0x8001_006C
0x8001_0070
0x8001_0074
0x8001_0078
0x8001_0080
0x8001_0084
0x8001_0088
0x8001_0090
RXDQBAdd
0x8001_0094
RXDQBLen
RXDQCurLe
0x8001_0096
0x8001_0098
RXDCurAdd
0x8001_009C
0x8001_00A0
RXStsQBAdd
0x8001_00A4
RXStsQBLen
RXStsQCurL
0x8001_00A6
Copyright 2007 Cirrus Logic
Table 9-3. Ethernet Register List
Name
RXCtl
MAC Receiver Control Register
TXCtl
MAC Transmitter Control Register
TestCtl
MAC Test Control Register
MIICmd
MAC MII Command Register
MIIData
MAC MII Data Register
MIISts
MAC MII Status Register
SelfCtl
MAC Self Control Register
IntEn
MAC Interrupt Enable Register
IntStsP
MAC Interrupt Status Preserve Register
IntStsC
MAC Interrupt Status Clear Register
Reserved
DiagAd
MAC Diagnostic Address Register
DiagDa
MAC Diagnostic Data Register
GT
MAC General Timer Register
FCT
MAC Flow Control Timer Register
FCF
MAC Flow Control Format Register
AFP
MAC Address Filter Pointer Register
MAC Individual Address Register, (shares address
IndAd
space with HashTbl)
MAC Hash Table Register, (shares address space with
HashTbl
IndAd)
GlIntSts
MAC Global Interrupt Status Register
GlIntMsk
MAC Global Interrupt Mask Register
GlIntROSts
MAC Global Interrupt Read Only Status Register
GlIntFrc
MAC Global Interrupt Force Register
TXCollCnt
MAC Transmit Collision Count Register
RXMissCnt
MAC Receive Miss Count Register
RXRuntCnt
MAC Receive Runt Count Register
BMCtl
MAC Bus Master Control Register
BMSts
MAC Bus Master Status Register
RXBCA
MAC Receive Buffer Current Address Register
MAC Receive Descriptor Queue Base Address Register
MAC Receive Descriptor Queue Base Length Register
MAC Receive Descriptor Queue Current Length
n
Register
MAC Receive Descriptor Current Address Register
RXDEnq
MAC Receive Descriptor Enqueue Register
MAC Receive Status Queue Base Address Register
MAC Receive Status Queue Base Length Register
MAC Receive Status Queue Current Length Register
en
Description
DS785UM1
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