Cirrus Logic EP93 Series User Manual page 245

Blink Control Registers
BlinkRate
31 30 29 28
15 14 13 12
Address: 0x8003_0040
Default: 0x0000_0000
Definition: Blink Rate Control register
Bit Descriptions:
RSVD:
RATE:
BlinkMask
31 30 29 28
15 14 13 12
Address: 0x8003_0044
Default: 0x0000_0000
Definition: Blink Mask register
This register is used in conjunction with the
which pixels that are fetched from SDRAM are blink pixels.
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
27 26 25
11 10 9
RSVD
Reserved - Unknown during read
Rate - Read/Write
The blink rate value that is written to this field controls the
number of video frames that occur before the LUT
addresses assigned to 'blink' change between masked
and unmasked (see
on/off blink cycle is controlled by this equation:
Blink Cycle = 2 x (1/VCLK) x HClkTotal x VLinesTotal x
(255 - BlinkRate)
27 26 25
RSVD
11 10 9
Copyright 2007 Cirrus Logic
24 23 22 21
RSVD
8 7 6 5
"Blink Function" on page
24 23 22 21
8 7 6 5
MASK
BlinkPattrn
EP93xx User's Guide
20 19 18 17
4 3 2 1
RATE
7-10). The
20 19 18 17
MASK
4 3 2 1
register to determine
7
16
0
16
0
7-63