Horz_Cnt3, Horz_Cnt4 Counters; Vert_Cnt3, Vert_Cnt4 Counters; Frame_Cnt3, Frame_Cnt4 Counters; Horz_Cntx (Pixel) Timing - Cirrus Logic EP93 Series User Manual

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
Assuming that pixel input value 0 is off, setting raster engine base + grayscale LUTx offset +
0x00, 0x20, 0x40, and 0x60 to all '0's ensures that a 0 pixel never turns on. Assuming that
7
pixel 7 is full on, setting raster engine base + grayscale LUTx offset + 0x1C, 0x3C, 0x5C, and
0x7C to all '1's ensures that the value is always on.
programming.

7.4.8.1 HORZ_CNT3, HORZ_CNT4 Counters

These free running counters increment after displaying each pixel.

7.4.8.2 VERT_CNT3, VERT_CNT4 Counters

These free running counters increment at the end of every vertical line.

7.4.8.3 FRAME_CNT3, FRAME_CNT4 Counters

These free running counters increment at the end of each frame.
The GrySclLUT supports 3-bit pixel input. Each of the pixel combinations can define a unique
combination of VERT, HORZ and FRAME counters, which provides for maximum flexibility in
defining the rate at which a given pixel is manipulated as it is being displayed on the screen.

7.4.8.4 HORZ_CNTx (pixel) timing

This timing is controlled by the HORZ_CNTx counter and will indicate what pixel count values
will cause a given pixel to be turned on. It is possible to have a pixel turned on for all HORZ
counts, zero HORZ counts, or a defined pattern of HORZ counts. This counter is incremented
by the pixel clock.

7.4.8.5 VERT_CNTx (line) timing

This timing is controlled by the VERT_CNTx counters and will indicate what line count values
will cause a given pixel to be turned on. It is possible to have a pixel turn on for all VERT
counts, zero VERT counts, or a defined pattern of VERT counts. This counter is incremented
at the end of each line.

7.4.8.6 FRAME_CNTx timing

This timing is controlled by the FRAME_CNTx counters and will indicate when a full frame of
video has been displayed. It is possible to have a pixel turn on for all FRAME counts, zero
frame counts, or a combination of frame counts. This counter is incremented at the end of
each frame.
The GrySclLUT combines all of the above information into a single table. In this way, it is
possible to define a pixel to be on in all conditions (all HORZ, VERT, and FRAME counts),
zero conditions, or any combination.
7-16
Table 7-6
Copyright 2007 Cirrus Logic
shows the format for
DS785UM1