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Cirrus Logic CS485 Series User Manual

32-bit audio dsp family
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CS485xx
32-bit Audio DSP Family
CS485xx
H ardwa re Us er 's Manual
Copyright 2009 Cirrus Logic
AUG '09
DS734UM7
http://www.cirrus.com

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Summary of Contents for Cirrus Logic CS485 Series

  • Page 1 CS485xx 32-bit Audio DSP Family CS485xx H ardwa re Us er ’s Manual Copyright 2009 Cirrus Logic AUG ’09 DS734UM7 http://www.cirrus.com...
  • Page 2 Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, Cirrus Extra Surround, Cirrus Original Multichannel Surround, Cirrus Original Surround, and Cirrus Framework are trademarks of Cirrus Logic All other brand and product names in this document may be trademarks or service marks of their respective owners.

  • Page 3: Table Of Contents

    3.2 Serial Control Port Configuration..........3-1 3.2.1 I C Port...........................3-2 3.2.2 I C System Bus Description ...................3-3 DS734UM7 Copyright 2009 Cirrus Logic...

  • Page 4: Contents

    8.2 Pin Description.............8-10 8.2.1 Power and Ground .......................8-10 8.2.1.1 Power......................8-10 Copyright 2009 Cirrus Logic DS734UM7...

  • Page 5: Figures

    Figure 3-13. Block Diagram of SPI System Bus ..................3-15 Figure 3-14. SPI Address and Data Bytes ....................3-16 Figure 3-15. SPI Write Flow Diagram ......................3-18 Figure 3-16. SPI Read Flow Diagram ......................3-19 Figure 3-17. Sample Waveform for SPI Write Functional Timing ...............3-21 DS734UM7 Copyright 2009 Cirrus Logic...
  • Page 6 Figure 8-9. PLL Filter Topology ........................8-12 Figure 8-10. Crystal Oscillator Circuit Diagram ..................8-13 Figure 8-11. 48-Pin LQFP Pin Layout of CS48560 ..................8-15 Figure 8-12. 48-Pin LQFP Pin Layout of CS48540 ..................8-16 Figure 8-13. 48-Pin LQFP Pin Layout of CS48520 ..................8-17 Copyright 2009 Cirrus Logic DS734UM7...
  • Page 7 Table 6-10. S/PDIF Transmitter Configuration ...................6-10 Table 7-1. Digital Audio Output (DAO) Pins ....................7-1 Table 8-1. Core Supply Pins ........................8-10 Table 8-2. I/O Supply Pins .........................8-10 Table 8-3. Core and I/O Ground Pins ......................8-11 Table 8-4. PLL Supply Pins ........................8-11 DS734UM7 Copyright 2009 Cirrus Logic...
  • Page 8 Table 8-7. DSP Core Clock Pins ........................8-13 Table 8-8. Reset Pin ...........................8-14 Table 8-9. Hardware Strap Pins .........................8-14 Table 8-10. Pin Assignments of CS48560 ....................8-18 Table 8-11. Pin Assignments of CS48540 ....................8-19 Table 8-12. Pin Assignments of CS48520 ....................8-20 viii Copyright 2009 Cirrus Logic DS734UM7...

  • Page 9: Chapter 1. Introduction

    Port for High-resolution Audio • Customer Software Security Keys • GPIO Support for All Common Sub-circuits • Large On-chip X,Y, and Program RAM & ROM • Hardware Watchdog Timer • Dual Clock Domains on Audio Inputs Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 10: Figure 1-1. Cs48560 Chip Functional Block Diagram

    Stereo Audio Output DAO2 Stereo Audio Output Decryptor Serial Control Port Programmable Interrupt Controller Timers DMA Bus DMA Controller with 8 Channels GPIOs Clock Manager and PLL Peripheral Bus Figure 1-1. CS48560 Chip Functional Block Diagram DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 11: Figure 1-2. Cs48540 Chip Functional Block Diagram

    Accumulators DAO2 Stereo Audio Output Decryptor Serial Control Port Programmable Interrupt Controller Timers DMA Bus DMA Controller with 8 Channels GPIOs Clock Manager and PLL Peripheral Bus Figure 1-2. CS48540 Chip Functional Block Diagram Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 12: Figure 1-3. Cs48520 Chip Functional Block Diagram

    ® The CS485xx supports master-mode interface on the serial control port to interface to SPI™ and I serial FLASH chips, thus allowing products to be field upgraded as new audio algorithms are developed. DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 13: Code Overlays

    "Code Overlays". Please contact your local Cirrus Logic Sales representative for more information. 1.2 Code Overlays The suite of software available for the CS485xx family consists of an operating system (OS) and a library of overlays.

  • Page 14: Functional Overview Of The Cs485Xx Chip

    S-compatible format. The port supports sample rates (Fs) as high as 192 kHz. The port can be configured to support two independent clock domains. The audio samples are stored in up to 12 channel DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 15: Digital Audio Input (Dai) Controller

    C or SPI specification. The port uses the SCP_IRQ pin to indicate that a read message is ready for the host. The port uses the SCP_BSY pin to warn the host to pause communication. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 16: Serial Flash Controller

    Clock (REFCLK). While operating in this mode, the OVFS clock can still be divided off the VCO so the PLL can be tested. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1. DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 17: Programmable Interrupt Controller

    §§ 1. The “§§” symbol is used throughout this manual to indicate the end of the text flow in a chapter. Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 18 Functional Overview of the CS485xx Chip CS485xx Hardware User’s Manual DS734UM7 Copyright 2009 Cirrus Logic, Inc. 1-10...

  • Page 19: Chapter 2. Operational Modes

    Slave and Master boot modes. Control Bus System Host Controller (Master) CS4953xx (Slave) Slave Boot External Memory Bus External ROM (Slave) CS4953xx (Master) Master Boot Figure 2-1. Operation Mode Block Diagrams Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 20: Operational Mode Selection

    (overlays) for certain processing tasks. Slave booting the CS485xx CS485xx requires loading multiple overlays - differing from previous Cirrus Logic Audio DSP families (that is, CS493xx, CS494xxx). Please refer to AN298, “ Firmware User’s Manual” regarding more CS485xx information on the breakdown of processing tasks for each overlay.

  • Page 21: Slave Boot

    AN298, “ Firmware User’s Manual”. CS485xx 2.3.2 Performing a Slave Boot Figure 2-2 shows the steps taken during a Slave Boot. The procedure is discussed in Section 2.3.2.1. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 22: Figure 2-2. Slave Boot Sequence

    WRITE_* (SOFT_RESET) READ_* (MSG) MSG ==APP_START EXIT (ERROR) SEND HARDWARE CONFIGURATIONS * is replaced with SPI, SEND FIRMWARE I2C, etc. depending on CONFIGURATIONS the communication protocol used. WRITE_* (KICKSTART) DONE Figure 2-2. Slave Boot Sequence DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 23: Slave Boot Procedure

    The application code user’s guide for each application provides a list of all pertinent configuration messages. 14.Send the KICKSTART message(s). The application locks the PLL and begins processing CS485xx audio after receiving this message. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 24: Boot Messages

    Note that there is a unique {ID} for every.uld file. Table 2-4. Boot Read Messages from CS485xx MNEMONIC VALUE BOOT_START 0x00000001 BOOT_SUCCESS 0x00000002 APP_START 0x00000004 BOOT_ERROR_CHECKSUM 0x000000FF INVALID_BOOT_TYPE 0x000000FE BOOT_FAILURE 0x000000F8 APPLICATION_FAILURE 0xF0{ID}0000 DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 25: Master Boot Procedure

    Currently this mode is not used for any applications. Start RESET ( Low) Set HS[4:0 ] Pins For Operational Mode RESET ( High) Done Figure 2-3. Master Boot Sequence Flowchart Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 26: Softboot

    SOFTBOOT_ACK 0x00000005 2.5.2 Softboot Procedure Figure 2-4 describes the Softboot procedure. This is a step-by-step guideline that can be used as an aid in developing the system controller code required to drive the CS485xx DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 27: Softboot Steps

    Step 2. Please note that this includes re-downloading all hardware and software configurations for the overlays. CS485xx 2.5.2.2 Softboot Example Figure 2-5 is an example flow diagram and step-by-step description of the Softboot procedure based on the SLAVE_BOOT procedure described earlier. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 28: Figure 2-5. Soft Boot Example Flowchart

    2. Wait for IRQ low. The host then waits for SCP_IRQ to go low. If the TIMEOUT period has been reached, the host should exit. If the IRQ pin is LOW, proceed to step 3. DS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-10...
  • Page 29 15.Send Software Configuration messages.The software configuration messages are specific to each application. The application code User’s Guide for each application provides a list of all pertinent configuration messages. 16.Send the KICKSTART message. The begins processing audio after receiving this CS485xx message. 2-11 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 30: Low Power Mode

    8. Read the APP_START message (0x00000004). 9. Send Hardware Configuration messages. 10.Send Software Configuration messages. 11.Send the KICKSTART messages. Figure 2-6 shows a flowchart of the steps used to exit Low Power mode. DS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-12...

  • Page 31: Figure 2-6. Flowchart Of Steps Used To Exit Low Power Mode

    READ_* (MSG) MSG== EXIT (ERROR) BOOT_SUCCESS WRITE_* (SOFT_RESET) READ_* (MSG) MSG== EXIT (ERROR) APP_START SEND HARDWARE CONFIGURATIONS SEND SOFTWARE CONFIGURATIONS WRITE_* (KICKSTART) DONE Figure 2-6. Flowchart of Steps Used to Exit Low Power Mode 2-13 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 32: Table 2-8. Wakeup_Uld Options And Values

    0xffffffff 0x427a0e9b 0x08004409 0x00000002 0x00000001 0xb485aa01 WAKEUP_P4.ULD0x 0x01000359 0x00000001 0x00000000 0xffffffff 0x427a0e9a 0x08004409 0x00000002 0x00000002 0xb485aa01 WAKEUP_P6.ULD 0x01000359 0x00000001 0x00000000 0xffffffff 0x427a0e99 0x08004409 0x00000002 0x00000003 0xb485aa01 WAKEUP_P8.ULD 0x01000359 0x00000001 0x00000000 0xffffffff 0x427a0e98 §§ DS734UM7 Copyright 2009 Cirrus Logic, Inc. 2-14...

  • Page 33: Chapter 3. Serial Control Port

    0x00. Please see Chapter 2, "Operational Modes" for additional details on configuring CS485xx ports and communication modes. Procedures for configuring the serial control port for SPI and I C communication modes are provided in this section. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 34: I 2 C Port

    7 6 5 4 3 2 1 0 SCP_SDA LSB (Byte 0) Byte1 Byte 2 MSB (Byte 3) LSB (Byte 0) Byte1 Byte 2 MSB (Byte 3) Figure 3-1. Serial Control Port Internal Block Diagram DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 35: I 2 C System Bus Description

    SCP_SDA Figure 3-2. Block Diagram of I C System Bus Table 3-1 shows the signal names, descriptions, and pin number of the signals associated with the I C Serial Control Port on the CS485xx. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 36: I 2 C Bus Dynamics

    Start condition is generated instead of a Stop condition. In this respect, the Start and repeated Start conditions are functionally identical. Start Stop SCP_CLK SCP_CLK SCP_SDA SCP_SDA Figure 3-3. I C Start and Stop Conditions DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 37: Figure 3-4. I 2 C Address With Ack And Nack

    SCP_SDA line high (NACK). The protocol on the last byte, however, is different. When the master receives the last byte, it signals the end of the data to the slave by allowing SCP_SDA to float high (NACK). Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 38: Figure 3-5. Data Byte With Ack And Nack

    SCP_CLK line low to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases SCP_CLK. DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 39: I 2 C Messaging

    C writing situation. The flow diagram shown in Figure 3-8 below, illustrates the sequence of events that define the I C write protocol for SCP. This protocol is discussed in the high-level procedure in Section 3.2.2.3.1. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 40: Figure 3-8. I 2 C Write Flow Diagram

    CS485xx should be re-booted. A NACK should never happen here. 4. The master should then clock one data byte into the device, most-significant bit first. 5. The CS485xx (slave) will (and must) acknowledge (ACK) each byte that it receives which means that DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 41: Performing A Serial I C Read

    4-byte words. The flow diagram shown in Figure 3-9 illustrates the sequence of events that define the I C read protocol for SCP. This protocol is discussed in the high-level procedure in Section 3.2.2.4.1. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 42: Figure 3-9. I 2 C Read Flow Diagram

    SCP_SDA == ACK? READ DATA BYTE SEND ACK BYTES READ = 4? SCP_IRQ LOW? SEND NACK SEND I2C STOP: DRIVE SCP_SDA HIGH WHILE SCP_CLK IS HIGH Figure 3-9. I C Read Flow Diagram DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-10...
  • Page 43 In other words, all data should be read out of the chip until SCP_IRQ signals the last byte by going high. 3-11 Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 44 Start Stop SCP_CLK SCP_SDA 7-bit Address Data Byte 3 (MSB) Data Byte 2 Data Byte 1 Data Byte 0 (LSB) Figure 3-10. Sample Waveform for I C Write Functional TIming Note: The I C slave is always responsible for driving the ACK for the address byte. Start Stop SCP_CLK...

  • Page 45: Spi Port

    MSB (Byte 3) Figure 3-12. SPI Serial Control Port Internal Block Diagram Table 3-2 shows the signal names, descriptions, and pin number of the signals associated with the SPI Serial Control Port on the CS485xx. 3-13 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 46: Spi System Bus Description

    SCP_MOSI (Master Out/Slave In) and SCP_MISO (Master In/Slave Out) are bidirectional lines that change their behavior depending on whether the device is operating in master or slave mode. Only the master can drive the MOSI signal while only the slave can drive the MISO signal. 3-14 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 47: Spi Bus Dynamics

    CS485xx (R/W = 1, Address = 0x81), then the master will drive the SCP_CLK signal and read the SCP_MISO signal with the data bytes from the CS485xx. 3-15 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 48: Figure 3-14. Spi Address And Data Bytes

    A falling edge of the SCP_BSY signal indicates the master must halt transmission. Once the SCP_BSY signal goes high, the suspended transaction may continue. The host must obey the SCP_BSY pin or control data will be lost. DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-16...

  • Page 49: Spi Messaging

    The example shown in this section can be generalized to fit any SPI write situation. The flow diagram shown in Figure 3-15 , illustrates the sequence of events that define the SPI write protocol. This protocol is discussed in the high-level procedure in Section 3.3.1.3.1. 3-17 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 50: Performing A Serial Spi Read

    Information provided in this section is intended as a functional description indicating how an external device (Master) performs an SPI read from the CS485xx (slave). The system designer must ensure that all timing constraints of the SPI read cycle are met (see the CS485xx datasheet for timing specifications). DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-18...

  • Page 51: Figure 3-16. Spi Read Flow Diagram

    SCP_CLK and data transitions occur on the falling edge of SCP_CLK. The serial clock should be held low so that eight transitions from low-to-high-to-low will occur for each byte. 3-19 Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 52 5. If SCP_IRQ is still low after 4 bytes, then proceed to step 4 and read another 4 bytes out of the CS485xx slave. 6. If SCP_IRQ is high, the SCP_CS line of CS485xx should be driven high to end the read transaction. DS734UM7 Copyright 2009 Cirrus Logic, Inc. 3-20...

  • Page 53: Figure 3-17. Sample Waveform For Spi Write Functional Timing

    SCP_CS SCP_CLK SCP_MOSI 7-bit Address Data Byte 3 (MSB) Data Byte 2 Data Byte 1 Data Byte 0 (LSB) Figure 3-17. Sample Waveform for SPI Write Functional Timing S C P _ C S S C P _ C L K S C P _ M O S I 7 - b i t A d d r e s s S C P _ M I S O...
  • Page 54 In other words, all data should be read out of the chip until SCP_IRQ signals the last byte by going high as described above. §§ 3-22 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 55: Chapter 4. Digital Audio Input Interface

    • Up to 32-bit Data Widths • Sample Rates up to 192 kHz • Two Simultaneous Audio Streams with Different Sample Frequencies (Fs) for Dual-path Processing Support • 2, 4, or 6 Channels on a Single Pin (DAI_DATAx) Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 56: Dai Pin Description

    DAI2_DATA0 in dual-clock domain mode. DAI2_SCLK Input DAI2_SCLK is the bit clock input for the serial PCM audio data on DAI_DATA[5:0] in single-clock domain mode. DAI2_DATA0 or PCM Audio Input Data Input DAI1_DATA4 DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 57: Supported Dai Functional Blocks

    DAI1_DATA0 DAI1_DATA1 DAI_LRCLK1 DAI1_DATA1 DAI_SCLK1 DAI1_DATA2 DAI1_DATA2 DAI2_DATA0 DAI_LRCLK2 DAI2_DATA0 DAI_SCLK2 Figure 4-2. 8-Channel DAI Port Block Diagram Figure 4-3 shows the functional block diagram of the features currently supported with the CS48520 DAI. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 58: Single Clock Domain - 12 Channel Input

    The DAI can also be configured to accept up to 12 channels of linear PCM audio (6 serial audio data inputs) by converting DAI1_LRCLK into a data pin (DAI1_DATA5). Consequently, there is only one possible clock domain (DAI2_LRCLK/SCLK). DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 59: Digital Audio Formats

    DAIn_LRCLK, and is valid on the rising edge of DAIn_SCLK. For the I S format, the left subframe is presented when DAIn_LRCLK is low, and the right subframe is presented when DAIn_LRCLK is high. Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 60: Left-Justified Format

    Where A, B, C, D, E, F, G, and H are the parameters used to fully define the input port. The parameters are defined as follows: A - Data Format B - SCLK Polarity C - LRCLK Polarity. DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 61: Table 4-2. Input Data Format Configuration (Input Parameter A)

    S 24-bit 0x81400012 0x01001F00 0x81800013 0xFFFF0000 0x81400013 0x01001F00 0x81800014 0xFFFF0000 0x81400014 0x01001F00 0x81800010 0xFEEF0000 0x81400010 0x00001F00 0x81800011 0xFEEF0000 0x81400011 0x00001F00 0x81800012 0xFEEF0000 Left-Justified 24-bit 0x81400012 0x00001F00 0x81800013 0xFEEF0000 0x81400013 0x00001F00 0x81800014 0xFEEF0000 0x81400014 0x00001F00 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 62: Table 4-3. Input Sclk Polarity Configuration (Input Parameter B)

    (i.e. Left) 0xFFDFFFFF 0x81800013 0xFFDFFFFF 0x81800014 0xFFDFFFFF 0x81400010 0x00200000 0x81400011 0x00200000 LRCLK=Low indicates Channel 1 0x81400012 (i.e. Right) 0x00200000 0x81400013 0x00200000 0x81400014 0x00200000 Note: The.D Value, DAI Mode, is not supported on the CS485xx platform. DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 63: Table 4-5. Dai2_Data Clock Source (Input Parameter E)

    0x81400015 0x0008D100 CS48560 0x81800015 0xFFF8D100 Table 4-8. DAII TDM (Input Parameter H) H Value HEX Message DAI TDM Source 0x81800015 0xFFF00000 0x81000010 0x01101F00 0x81000011 0x01103F20 DAI1_D0 (Pin 10) 0x81000012 0x01105F40 0x81000013 0x01107F60 0x81000014 0x01109F80 Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 64 DAI Hardware Configuration CS485xx Hardware User’s Manual a. TDM (Time Division Multiplex) is only available on the CS48560 product. b. Accepts a maximum of 12 channlels of input. §§ DS734UM7 Copyright 2009 Cirrus Logic, Inc. 4-10...

  • Page 65: Digital Audio Input Port Description

    The CS48560 supports internal conversion of DSD data to PCM which can then be processed by the DSP. Note: If DSD functionality is needed in a system design, contact your Cirrus Logic FAE. 5.1 Digital Audio Input Port Description The CS48560 DSD port is designed to accept DSD audio data from up to 6 pins simultaneously (6 channels total).

  • Page 66: Figure 5-1. Dsd Port Block Diagram On Cs48560

    Digital Audio Input Port Description CS485xx Hardware User’s Manual DSD0 DSD_DATA0 DSD1 DSD_DATA1 DSD2 DSD_DATA2 DSD3 DSD_DATA3 DSD_CLK DSD4 DSD_DATA4 DSD5 DSD_DATA5 Figure 5-1. DSD Port Block Diagram on CS48560 §§ DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 67: Chapter 6. Digital Audio Output Interface

    Note: DAO1_DATA2 is not available on CS48520 DAO1_DATA3/XMTA Digital Audio Output Output DAO2_DATA0 Digital Audio Output Output Digital Audio Output Note: DAO2_DATA1 is not DAO2_DATA1 Output available on CS48520 or CS48540. DAO_MCLK Master Clock Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 68: Figure 6-1. Cs48560 Dao Block Diagram

    • DAOn_DATA[n] are the data outputs and are typically configured for outputting two channels of I or left-justified PCM data. DAO1_DATA0 DAO1_DATA1 DAO1_DATA2 DAO1_DATA3, XMTA DAO1_DATA3 SPDIF ENCODER DAO2_DATA0 DAO2_DATA1 DAO_MCLK DAO_SCLK DAO_LRCLK Figure 6-1. CS48560 DAO Block Diagram DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 69: Figure 6-2. Cs48540 Dao Block Diagram

    CS485xx Hardware User’s Manual DAO1_DATA0 DAO1_DATA1 DAO1_DATA2 SPDIF XMTA ENCODER DAO2_DATA0 DAO_MCLK DAO_SCLK DAO_LRCLK Figure 6-2. CS48540 DAO Block Diagram DAO1_DATA0 SPDIF XMTA ENCODER DAO2_DATA0 DAO_MCLK DAO_SCLK DAO_LRCLK Figure 6-3. CS48520 DAO Block Diagram Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 70: Supported Dao Functional Blocks

    L e ft C h a n n e l R ig ht C h a n n el DAO_LRCLK DAO_SCLK DAO_DATA +3 +2 Figure 6-5. Left-justified Digital Audio Formats (Rising Edge Valid DAO_SCLK) DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 71: One-Line Data Mode Format (Multichannel)

    DAO Modes (MCLK, LRCLK and Hex Message Value SCLK) 0x8140001C DAO_MCLK - Slave 0x00002000 0 (Default) DAO_LRCLK - Slave 0x8140001D DAO_SCLK - Slave 0x00002000 0x8180001C DAO_MCLK - Slave 0xFFFFDFFF DAO_LRCLK - Master 0x8180001D DAO_SCLK - Master 0xFFFFDFFF Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 72: Table 6-3. Dao1 & Dao2 Clocking Relationship Configuration (Parameter B)

    DAO_LRCLK = DAO_SCLK / 256 = FS 0xFFFFFF8F 0x8140001C 0x00000060 0x8100002D 0x00007701 DAO_MCLK = 128 FS 0x8100002E 0x00007701 DAO_SCLK = DAO_MCLK / 2 = 64 FS 0x8180001C DAO_LRCLK = DAO_SCLK / 64 = FS 0xFFFFFF8F 0x8140001C 0x00000020 DS734UM7 Copyright 2009 Cirrus Logic, Inc.
  • Page 73 DAO_LRCLK = DAO_SCLK / 96 = FS 0xFFFFFF8F 0x8140001C 0x00000030 0x8100002D 0x00077201 DAO_MCLK = 384 FS 0x8100002E 0x00077201 DAO_SCLK = DAO_MCLK / 2 = 192 FS 0x8180001C DAO_LRCLK = DAO_SCLK / 192 = FS 0xFFFFFF8F 0x8140001C 0x00000050 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 74: Table 6-5. Output Data Format Configuration (Parameter D)

    0x00000000 0x81000024 0x00000000 Left Justified 32-bit 0x81000025 0x00000000 0x81000026 0x00000000 0x81000027 0x00000000 0x8180001c 0xFFFFFBFF 0x8180001d 0xFFFFFBFF 0x81000020 0x00011701 0x81000021 0x00000001 0x81000022 0x00000001 0x81000023 0x00000001 TDM 32-bit 0x81000024 0x00011701 0x81000025 0x00000001 0x81000026 0x00000001 0x81000027 0x00000001 DS734UM7 Copyright 2009 Cirrus Logic, Inc.

  • Page 75: S/Pdif Transmitter

    DAO port. XMTA S/PDIF output pin on the CS48560 can be configured as: DAO_DATA3/ • I S output - Default • S/PDIF Transmitter - Sent configuration from Table 6-10 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 76: Table 6-9. S/Pdif Transmitter Pins

    Table 6-9. S/PDIF Transmitter Pins LQFP-48 Pin Name Pin Description Pin # Type DAO_DATA3/XMTA S/PDIF Audio Output A Output Table 6-10. S/PDIF Transmitter Configuration Description Hex Message Enable S/PDIF Audio Output A on 0x8100001e DAO_DATA3/XMTA 0x00005080 §§ DS734UM7 Copyright 2009 Cirrus Logic, Inc. 6-10...
  • Page 77 The PLL is controlled by the clock manager in the DSP O/S application software. AN298, CS485xx Firmware User’s Manual should be referenced regarding what CLKIN input frequency and PLL multiplier values are supported. Figure 7-1 shows the schematic of the CS485xx crystal oscillator. Copyright 2008 Cirrus Logic, Inc. DS734UM7...
  • Page 78 Hardware configuration messages are used to configure the XTAL_OUT divider. 7.2.1 Crystal Oscillator Hardware Configuration Messages Table 7-2 shows the command for configuring the XTAL_OUT pin for Divide-by-2 operation. Table 7-2. XTAL_OUT Configuration Description Hex Message 0x81400042 XTAL_OUT Divide-by-2 0x00000800 §§ DS734UM7 Copyright 2008 Cirrus Logic, Inc.

  • Page 79: Introduction

    GPIO2 DAI1_DATA3 GPIO3 DAO1_DATA1 GPIO4 DAO1_DATA2 GPIO5 DAO1_DATA3 GPIO6 DAO2_DATA0 GPIO7 DAO2_DATA1 GPIO8 SCP_CS GPIO9 SCP_MOSI GPIO10 SCP_MISO GPIO11 SCP_CLK GPIO12 SCP_IRQ GPIO13 SCP_BSY GPIO14 DAI2_LRCLK GPIO15 DAI2_SCLK GPIO16 DAI1_DATA0 GPIO17 DAI2_DATA0 GPIO18 DAO_MCLK Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 80: Watchdog Timer Description

    Watchdog Alarm Indicator. The GPIO used for the Watchdog Alarm Indicator is selected during the configuration of application code on the CS485xx. The details of selecting a Watchdog GPIO can be found in AN298. §§ Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 81: Typical Connection Diagrams

    R = (Z – 20), where 20 represents the source impedance of the CS485xx drivers. The typical connection diagrams show “0.1uF x 3” to indicate that 1 decoupling capacitor should be placed next to each power pin. Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 82 Figure 9-1. SPI Slave, 10 channels of Digital Audio Input, All Audio Clocks Synchronous to S/PDIF RX...
  • Page 83 Figure 9-2. I C Slave, 10 Channels of Digital Audio Input, Dual Clock Domains, Output Audio Clocks Synchronous to HDMI Rx...
  • Page 84 Figure 9-3. I C Slave, 12 Channels of Digital Audio Input, Single Clock Domain, All Audio Clocks Synchronous to XTAL_OUT...
  • Page 85 Figure 9-4. I C master, 10 Channels of Digital Audio Input, All Audio Clocks Synchronous to S/PDIF Rx...
  • Page 86 Figure 9-5. SPI Slave, 10 Channels of Digital Audio Input, All Audio Clocks Synchronous to S/PDIF Rx...
  • Page 87 Figure 9-6. SPI Slave, 10 Channels of Digital Audio Input, Dual Clock Domains, Output Audio Clocks Synchronous to HDMI Rx...
  • Page 88 Figure 9-7. SPI Slave, 12 Channels of Digital Audio Input, Single Clock Domain, All Audio Clocks Synchronous to XTAL_OUT...
  • Page 89 Figure 9-8. SPI Master, 10 Channels of Digital Audio Input, All Audio Clocks Synchronous to S/PDIF Rx.

  • Page 90: Pin Description

    Input This powers all internal logic and the on-chip SRAMs and ROMs VDD3 Table 9-2. I/O Supply Pins LQFP-48 Pin Name Pin Description Pin # Type VDDIO1 VDDIO2 Input 3.3V I/O supply VDDIO3 DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-10...

  • Page 91: Ground

    Pin Description Pin # PLL supply. This voltage must be 3.3V. This VDDA Input must be clean, noise-free analog power. PLL ground. This ground should be as noise- GNDA Input free as possible. 9-11 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 92: Pll

    9.4 Control The CS485xx supports 2 control interface protocols (SPI and I C), one slave mode for each protocol, and multiple master modes. DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-12...

  • Page 93: Operational Mode

    Hardware Strap Mode Select Input The state of these pins is latched at the rising edge of RESET. The boot ROM uses the state of these pins to select the boot mode. 9-13 Copyright 2009 Cirrus Logic, Inc. DS734UM7...

  • Page 94: 48-Pin Lqfp Pin Assigments

    VDD3 GNDIO2 48 LQFP XTAL_OUT GPIO15, DAI2_SCLK GPIO14, DAI2_LRCLK VDD1 GNDA GPIO17, DAI2_DATA0, DSD4 PLL_REF_RES GPIO2, DAI1_DATA3, TM3, DSD3 GPIO1, DAI1_DATA2, TM2, DSD2 VDDA (3.3V) Figure 9-10. 48-Pin LQFP Pin Layout of CS48560 DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-14...
  • Page 95 DAO_LRCLK DAO1_DATA0, HS0 GPIO13, SCP_BSY#, EE_CS# CS48540 VDD3 GNDIO2 48 LQFP XTAL_OUT GPIO15, DAI2_SCLK GPIO14, DAI2_LRCLK VDD1 GNDA GPIO17, PLL_REF_RES GPIO2 GPIO1, DAI1_DATA2 VDDA (3.3V) Figure 9-11. 48-Pin LQFP Pin Layout of CS48540 9-15 Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 96 DAO_LRCLK DAO1_DATA0, HS0 GPIO13, SCP_BSY#, EE_CS# CS48520 VDD3 GNDIO2 48 LQFP XTAL_OUT GPIO15, DAI2_SCLK GPIO14, DAI2_LRCLK VDD1 GNDA GPIO17, DAI2_DATA0 PLL_REF_RES GPIO2 VDDA (3.3V) GPIO1 Figure 9-12. 48-Pin LQFP Pin Layout of CS48520 DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-16...

  • Page 97: Pin Assignments

    1. SPI Mode Master Data Output/Slave Data 3.3V (5V tol) Input BiDi/OD GPIO10 General Purpose Input/Output 1. SCP_MISO 1. SPI Mode Master Data Input/Slave Data 3.3V (5V tol) 2. SCP_SDA Output 2. I C Mode Master/Slave Data IO 9-17 Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 98 1. Hardware Strap Mode Select. 3.3V (5V tol) BiDi DAO_LRCLK PCM Audio Sample Rate 3.3V (5V tol) Clock GNDD3 Core ground BiDi DAO_SCLK PCM Audio Output Bit Clock 3.3V (5V tol) VDDIO2 I/O power supply voltage 3.3V DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-18...
  • Page 99 Rate (Left/Right) Clock GNDIO1 I/O ground DAI1_SCLK PCM Audio Input Bit Clock 3.3V (5V tol) GNDD2 Core ground BiDi GPIO16 General Purpose Input/Output 1. DAI1_DATA0 1. Digital Audio Input Data 3.3V (5V tol) 9-19 Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 100 Input/Crystal Oscillator Input Reference Clock Input/Crystal 3.3V (5V tol) Oscillator Input Crystal Oscillator Output 3.3V GNDA PLL ground 3.3V PLL_REF_RES Current Reference Output for 3.3V PLL. Connect to resistor. VDDA PLL power. 3.3V DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-20...

  • Page 101: Revision History

    9-1. Added Section 2.6. March 11, 2009 Updated Table 6-8. Added Chapter 7, "Crystal Oscillator and System Clocking". August 05,, 2009 Updated Left-Justified 24-bit configuration settings in Table 4-2. Modified Section 9.3. §§ 9-21 Copyright 2009 Cirrus Logic, Inc. DS734UM7...
  • Page 102 Revision History CS485xx Hardware User’s Manual DS734UM7 Copyright 2009 Cirrus Logic, Inc. 9-22...

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