Cirrus Logic EP93 Series User Manual page 367

Bit Descriptions:
RSVD:
INT:
MII/PHY Access Register Descriptions
All PHY registers are accessed through the MII Command, Data and Status Registers. Write
operations are accomplished by writing the required data to the MII Data Register and then
writing the required Command to the MII Command Register (Opcode = 01, PhyAd = target
phy, RegAd = target register), which causes the Busy bit (MII Status) to be set. When the
Busy bit is clear, the write operation has been performed. Read operations are performed by
writing a read command to the MII Command register (Opcode = 10b, PhyAd = target phy,
RegAd = source register), which will also cause the Busy bit (MII Status) to be set. When the
read operation has been completed, the Busy bit is cleared and the read data is available in
the MII Data register.
MIICmd
31 30 29 28
15 14 13 12
OP
Address:
0x8001_0010 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
MII Command Register. Provides read-write access to the external PHY
registers using the MII command data port.
Bit Descriptions:
RSVD:
OP:
DS785UM1
Reserved. Unknown During Read.
Global interrupt force bit, write only, always reads zero.
Writing a one to this bit will set the Global Interrupt Status
bit, if it is enabled. Writing a zero has no effect.
27 26 25 24
11 10 9
RSVD
Reserved. Unknown During Read.
OPcode. This Opcode field defines the type of operation to
be performed to the appropriate PHY register.
10 - Read register
01 - Write register
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
23 22 21
RSVD
8 7 6 5
PHYAD
EP93xx User's Guide
20 19 18 17
4 3 2 1
REGAD
9
16
0
9-65