Cirrus Logic EP93 Series User Manual page 574

UART2
EP93xx User's Guide
15
UART2DMACtrl
31 30
15 14
Address:
Default:
Definition:
Bit Descriptions:
15-16
ILPDV:
29 28 27 26
13 12 11 10
0x808D_0028 - Read/Write
0x0000_0000
UART DMA Control Register
RSVD:
DMAERR:
TXDMAE:
RXDMAE:
Copyright 2007 Cirrus Logic
IrDA Low Power Divisor bits [7:0]. 8-bit low-power divisor
value. These bits are cleared to 0 at reset. The divisor
must be chosen so that the relationship
1.42 MHz < IrLPBaud16 < 2.12 MHz is maintained, which
results in a low power pulse duration of 1.41–2.11 μs
(three times the period of IrLPBaud16). The minimum
frequency of IrLPBaud16 ensures that pulses less than
one period of IrLPBaud16 are rejected, but that pulses
greater than 1.4 μs are accepted as valid pulses. Zero is
an illegal value. Programming a zero value will result
in no IrLPBaud16 pulses being generated.
25 24 23 22
RSVD
9 8 7 6
RSVD
Reserved. Unknown During Read.
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If "1",
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TX DMA interface enable. Setting to "1" enables the
private DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to "1" enables the
private DMA interface to the receive FIFO.
21 20 19 18
5 4 3 2
DMAERR
17 16
1 0
TXDMAE RXDMAE
DS785UM1