Vectored Interrupt Controller
EP93xx User's Guide
VIC Interrupt
6
6.1.3 Interrupt Details
Details of the interrupts described in
6-4
Name
Source
32
INT_EXT[0]
33
INT_EXT[1]
34
INT_EXT[2]
35
TINTR
36
WEINT
37
INT_RTC
38
INT_IrDA
39
INT_MAC
40
-
41
INT_PROG
42
CLK1HZ
43
V_SYNC
44
INT_VIDEO_FIFO
45
INT_SSP1RX
46
INT_SSP1TX
47
-
48
-
49
-
50
-
51
TC3UI
52
INT_UART1
53
SSPINTR
54
INT_UART2
55
INT_UART3
56
USHINTR
57
INT_PME
58
INT_DSP
59
GPIOINTR
60
I2SINTR
61
-
62
-
63
-
COMMRX
COMMTX
Copyright 2007 Cirrus Logic
Table 6-1. Interrupt Configuration
Watchdog Expired Interrupt
Ethernet MAC Interrupt
Raster Programmable Interrupt
Raster Video FIFO Interrupt
SSP Transmit Interrupt
TC3 under flow interrupt (Timer Counter 3)
Synchronous Serial Port Interrupt
Ethernet MAC PME Interrupt
GPIO Combined interrupt
I2S Block Combined interrupt
Table 6-1
are:
ARM Communication Channel Receive. When high,
COMMRX indicates that the communications channel
receive buffer contains data waiting to be read by the ARM
Core. Refer to the ARM Technical Reference Manual.
ARM Communication Channel Transmit. When high
COMMTX indicates that the communications channel
transmit buffer is empty. Refer to the ARM Technical
Reference Manual.
Description
External Interrupt 0
External Interrupt 1
External Interrupt 2
64 Hz Tick Interrupt
RTC Interrupt
IrDA Interrupt
Reserved
1 Hz Clock Interrupt
Video Sync Interrupt
SSP Receive Interrupt
Reserved
Reserved
Reserved
Reserved
UART 1 Interrupt
UART 2 Interrupt
UART 3 Interrupt
USB Host Interrupt
ARM Core Interrupt
Unused
Unused
Unused
DS785UM1
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