Cirrus Logic EP93 Series User Manual page 457

HcInterruptStatus
31 30 29 28
RSVD OC
15 14 13 12
Address:
0x8002_000C
Default:
0x0000_0000
Definition:
Provides interrupt status information.
Bit Descriptions:
RSVD:
SO:
WDH:
SF:
RD:
UE:
DS785UM1
27 26 25 24
11 10 9 8
RSVD
Reserved. Unknown During Read.
SchedulingOverrun. This bit is set when the USB schedule
for the current Frame overruns and after the update of
HccaFrameNumber. A scheduling overrun will also cause
the SchedulingOverrunCount of HcCommandStatus to be
incremented.
WritebackDoneHead. This bit is set immediately after HC
has written HcDoneHead to HccaDoneHead. Further
updates of the HccaDoneHead will not occur until this bit
has been cleared. HCD should only clear this bit after it
has saved the content of HccaDoneHead.
StartofFrame. This bit is set by HC at each start of a frame
and after the update of HccaFrameNumber. HC also
generates a SOF token at the same time.
ResumeDetected. This bit is set when HC detects that a
device on the USB is asserting resume signaling. It is the
transition from no resume signaling to resume signaling
causing this bit to be set. This bit is not set when HCD sets
the USBRESUME state.
UnrecoverableError. This bit is set when HC detects a
system error not related to USB. HC should not proceed
with any processing nor signaling before the system error
has been corrected. HCD clears this bit after HC has been
reset.
Copyright 2007 Cirrus Logic
Universal Serial Bus Host Controller
23 22 21 20
RSVD
7 6 5 4
RHSC FNO UE
EP93xx User's Guide
19 18 17 16
3 2 1 0
RD SF WDH SO
11-17
11