Cirrus Logic EP93 Series User Manual page 227

HClkStrtStop
31 30 29 28
RSVD
15 14 13 12
RSVD
Address: 0x8003_001C
Default: 0x0000_0000
Definition: Horizontal Clock Active Start/Stop register
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
Bit Descriptions:
RSVD:
STOP:
STRT:
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
27 26 25 24
11 10 9 8
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HCLKEN signal becomes inactive
(stops). This indicates the end of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HCLKEN signal becomes active
(starts). This indicates the start of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
Copyright 2007 Cirrus Logic
23 22 21 20
STOP
7 6 5 4
STRT
Figure 7-9 and Figure
Figure 7-9 and Figure
EP93xx User's Guide
19 18 17 16
3 2 1 0
7-10. HCLKEN is an
7-10. HCLKEN is an
7-45
7