Cirrus Logic EP93 Series User Manual page 437

DAR_BASEx
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15 14 13 12
Address:
DAR_BASE0: Channel Base Address + 0x002C- Read/Write
DAR_BASE1: Channel Base Address + 0x0030 - Read/Write
Definition:
This register contains the base memory address to which the DMA controller
transfers data.
Bit Descriptions:
DAR_BASEx:
SAR_CURRENTx
31 30 29 28
15 14 13 12
Address:
SAR_CURRENT0: Channel Base Address + 0x0024 - Read Only
SAR_CURRENT1: Channel Base Address + 0x0028 - Read Only
Definition:
This is the Channel Current Source Address Register.
DS785UM1
27 26 25 24
DAR_BASEx
11 10 9 8
DAR_BASEx
x = 0 or 1 representing the double buffer per channel. This
register contains the base memory address to which the
DMA controller sends data. At least 1 of the DAR_BASEx
registers must be programmed before the ENABLE bit and
the START bit (in the case of software trigger M2M mode)
are set in the Control register, and also before the
corresponding BCRx register is programmed. The second
buffer descriptor can be programmed while the transfer
using the 'other' buffer is being carried out (thus reducing
software latency impact). When transferring from memory
to external peripheral, the DAR_BASEx will contain the
base address of the memory mapped device.
27 26 25 24
SAR_CURRENTx
11 10 9 8
SAR_CURRENTx
Copyright 2007 Cirrus Logic
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7 6 5 4
23 22 21 20
7 6 5 4
DMA Controller
EP93xx User's Guide
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3 2 1 0
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