Figure 28-1. System Level Gpio Connectivity - Cirrus Logic EP93 Series User Manual

GPIO Interface
EP93xx User's Guide
28
28-2
Mux
Controls
Port A
OE
8
Control
DATA
EP
Mux
Controls
Port B
OE
Control
DATA
EP
Mux
Controls
Port C
OE
Control
DATA
EP
Mux
Controls
Port D
OE
Control
DATA
EP
Mux
Controls
Port E
OE
Control
DATA
EP
Mux
Controls
Port F
OE
8
Control
DATA
EP
Mux
Controls
Port G
OE
8
Control
DATA
EP
Mux
Controls
Port H
OE
Control 8
DATA
EP

Figure 28-1. System Level GPIO Connectivity

Copyright 2007 Cirrus Logic
MUX_IO
8
MUX_IO
8
8
MUX_IO
8
8
MUX_IO
8
8
MUX_IO
8
8
MUX_IO
8
MUX_IO
8
MUX_IO
8
EGPIO[7:0]
EGPIO[15:8]
ROW[7:0]
COL[7:0]
IDEDA[2:0]
IDECS0n
IDECS1n
DIORn
RDLED
GRLED
VS2
READY
VS1
MCBVD2
MCBVD1
MCCD2
MCCD1
WP
DD[15:12]
SLA[1:0]
EEDAT
EECLK
DD[7:0]
DS785UM1