Cirrus Logic EP93 Series User Manual page 225

HActiveStrtStop
31 30 29 28
RSVD
15 14 13 12
RSVD
Address: 0x8003_0018
Default: 0x0000_0000
Definition: Horizontal Active period Start/Stop register
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
Bit Descriptions:
RSVD:
STOP:
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
The STOP value is the horizontal down counter value at
which the HSYNCn signal becomes inactive (stops). When
the Horizontal counter counts down to the STOP value,
the HSYNCn signal goes inactive. Please refer to video
signalling timing diagrams in
STRT:Start - Read/Write
The STRT value is the horizontal down counter value at
which the HSYNCn signal becomes active (starts). When
the Horizontal counter counts down to the STRT value, the
HSYNCn signal goes active (starts). Please refer to video
signalling timing diagrams in
27 26 25 24
11 10 9 8
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HACTIVE signal becomes inactive
(stops). This indicates the end of the active video portion
for the Horizontal line. Please refer to video signalling
timing diagrams in
is an internal block signal. The active video interval is
controlled by the logical OR of VACTIVE and HACTIVE.
Copyright 2007 Cirrus Logic
Figure 7-9
Figure 7-9
23 22 21 20
STOP
7 6 5 4
STRT
Figure 7-9 and
EP93xx User's Guide
and Figure 7-10.
and Figure 7-10.
19 18 17 16
3 2 1 0
Figure 7-10. HACTIVE
7-43
7