Cirrus Logic EP93 Series User Manual page 517

Definition:
The Refresh Timer register is used to specify the period between refresh
cycles.
Bit Descriptions:
RSVD:
Refcnt:
BootSts
31 30 29 28
15 14 13 12
Address: 0x8006_000C - Read Only
Default: 0x0000_0000
Definition:
When power on reset is asserted, the values of the boot mode option pins
shown in
latched values. This register can be read to determine which memory
configuration was used during the boot process.
Bit Descriptions:
RSVD:
ASDO:
Width:
DS785UM1
Reserved. - Unknown During Read
Refresh Count - Read/Write
The value written to this field specifies, in multiples of the
period of HCLK, the time period between refresh cycles.
For example, if the period of HCLK is 20 ns, this field
should be written to 0x320 (decimal 800) to generate a
16 ms refresh period. On reset, this field defaults to
0x0080 (decimal 128) to generate a 2.56 ms refresh
period, but it must be written during the SDRAM
initialization routine to the appropriate value for the
SDRAM devices. If this field is written to 0x0000, no
refresh cycles are issued.
27 26 25 24
RSVD
11 10 9 8
RSVD
Table 13-1 are latched. The Boot Status register reflects those
Reserved - Unknown During Read
Latched ASDO pin value - Read Only
Boot Media:
1 - SyncROM or SyncFLASH
0 - Asynchronous ROM
Boot memory bus Width - Read Only
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
23 22 21 20
7 6 5 4
EP93xx User's Guide
19 18 17 16
3 2 1 0
Latched Width
ASDO
13-21
13