Cirrus Logic EP93 Series User Manual page 357

TXCollCnt
31 30 29 28
15 14 13 12
Address:
0x8001_0070 - Read Only
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Transmit Collision Count Register
Bit Descriptions:
RSVD:
TXC:
RXMissCnt
31 30 29 28
15 14 13 12
Address:
0x8001_0074 - Read Only
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
DS785UM1
27 26 25 24
RSVD
11 10 9 8
TXC
Reserved. Unknown During Read.
Transmit Collision Count. The transmit collision count
records the total number of collisions experienced on the
transmit interface, including late collisions. When the most
significant bit of the count is set, an optional interrupt may
be generated. The register is cleared automatically
following a read and writing to the register will have no
effect.
27 26 25 24
RSVD
11 10 9 8
RMC
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
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7 6 5 4
23 22 21 20
7 6 5 4
EP93xx User's Guide
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