I 2 S Configuration And Status Registers; Table 21-9. I 2 S Configuration And Status Registers - Cirrus Logic EP93 Series User Manual

Bit Descriptions:
RSVD:
i2s_rx1_EN:
I2SRX2En
31 30 29 28
15 14 13 12
Address:
0x8082_006C - Read/Write
Default:
0x0000_0000
efinition:
D
RX2 Channel Enable
Bit Descriptions:
RSVD:
i2s_rx2_EN:
2
21.7.3 I S Configuration and Status Registers
Address
0x8082_0000
0x8082_0004
0x8082_0008
0x8082_000C
DS785UM1
Reserved. Unknown During Read. Must be written as "0".
RX1 Channel Enable
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read. Must be written as "0".
RX2 Channel Enable
2
Table 21-9. I S Configuration and Status Registers
Type Width Reset Value
R/W 7 0x0
R/W 7 0x0
R/W 20 0x12492
R/W 2 0x0
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
Name
Transmitter clock configuration
I2STXClkCfg
register.
Receiver clock configuration
I2SRXClkCfg
register
2
I S Global Status register. This
I2SGlSts
reflects the status of the 3 RX
FIFOs and the 3 TX FIFOs.
2
I2SGlCtrl
I S Global Control register.
2
I S Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
i2s_rx2_EN
Description
21-25
21