Cirrus Logic EP93 Series User Manual page 419

INTERRUPT
31 30 29 28
15 14 13 12
Address:
Channel Base Address + 0x0004 - Read/Write
Definition:
This is the interrupt status register. The register is read to obtain interrupt
status for enabled interrupts. An interrupt is enabled by writing the
corresponding bits in the CONTROL register.
Write this location once to clear the interrupt. (See Interrupt Register Bit
Descriptions for the bits where this rule applies.)
Bit Descriptions:
RSVD:
STALLInt:
NFBInt:
ChErrorInt:
DS785UM1
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read.
Indicates channel has stalled. This interrupt is generated
on a Channel State machine transition from ON to STALL
state, if STALLIntEn set. This is a critical interrupt as it
indicates that an over/underflow condition will occur as
soon as the peripheral's FIFO is full/empty. The interrupt is
cleared by either disabling the channel or writing a new
base address which will move the state machine onto the
ON state.
Indicates channel requires a new buffer. This interrupt
generated on a Channel State machine transition from
NEXT to ON state if NFBIntEn set. The interrupt is cleared
by either disabling the channel or writing a new base
address, which will move the state machine onto the next
state.
This interrupt is activated when the peripheral attached to
the DMA Channel detects an error in the data stream. The
peripherals signal this error by ending the current transfer
with a TxEnd/RxEnd error response. The interrupt is
cleared by writing either a "1" or a "0" to this bit.
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
ChErrorInt
DMA Controller
EP93xx User's Guide
19 18 17 16
3 2 1 0
0 NFBInt STALLInt
10-25
10