Hci Master Block; Usb State Control; Data Fifo; List Processor - Cirrus Logic EP93 Series User Manual

Universal Serial Bus Host Controller
EP93xx User's Guide

11.2.5.4 HCI Master Block

The HCI Master Block handles read/write requests to system memory that are initiated by the
List Processor while the Host Controller (HC) is in the operational state and is processing the
lists queued in by HCD. It generates the addresses for all the memory accesses, which is the
DMA functionality. The major tasks handled by this block are:
• Fetching Endpoint Descriptors (ED) and Transfer Descriptors (TD)
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• Read/Write endpoint data from/to system memory
• Accessing HC Communication Area (HCCA)
• Write Status and Retire TDs

11.2.5.5 USB State Control

This block implements:
• The USB operational states of the Host Controller, as defined in the OHCI Specification.
• It generates SOF tokens every 1 ms
• It triggers the List Processor while HC is in the operational states.

11.2.5.6 Data FIFO

This block contains a 64x8 FIFO to store the data returned by endpoints on IN tokens, and
the data to be sent to the endpoints on OUT Tokens. The FIFO is used as a buffer in case the
HC does not get timely access to the host bus.

11.2.5.7 List Processor

The List Processor processes the lists scheduled by HCD according to the priority set in the
operational registers.

11.2.5.8 Root Hub and Host SIE

The Root Hub propagates Reset and Resume to downstream ports and handles port connect
and disconnect. The Host Serial Interface Engine (HSIE) converts parallel to serial, serial to
parallel, Non-Return to Zero Interface (NRZI) encoding/decoding and manages USB serial
protocol.
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Copyright 2007 Cirrus Logic
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