Bus Bandwidth Requirements; Table 17-6. Irda Service Memory Accesses / Second - Cirrus Logic EP93 Series User Manual

IrDA
EP93xx User's Guide
To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less
than or equal to four times the frequency of PCLK:
If the IrDA SIR functionality is required, UARTCLK must have a frequency between 2.7 MHz
and 542.7 MHz to ensure that the low-power mode transmit pulse duration complies with the
IrDA SIR specification.
17

17.5.4.3 Bus Bandwidth Requirements

There are four different IrDA modes with different bandwidth requirements. Furthermore,
there are two basic ways of moving data to or from the IrDA FIFOs:
• Direct DMA interface - this permits byte-wide access to the IrDA without using the APB.
The DMA block will pack/unpack individual bytes so that it reads or writes full 32-bit
words rather than individual bytes.
• Accessing the IrDA via the APB - this requires APB/AHB bus bandwidth. Then, both a
read and write are required for each 32-bit data word.
Assuming most bytes in a packet are moved either via the DMA interface or via 32-bit word
accesses to the IrDA controller on the APB,
number of memory accesses per second to service IrDA TX or RX:
Note that the SIR mode bit rate is a worst case value.
17-22

Table 17-6. IrDA Service Memory Accesses / Second

Infrared Mode Bit Rate (bits / second)
SIR
Slow MIR
Fast MIR
FIR
≤ ×
F 4 F
UARTCLK PCLK
Table 17-6
115,200
576,000
1,152,000
4,000,000
Copyright 2007 Cirrus Logic
indicates the maximum average
Bus accesses / second
DMA APB
3,600 7,200
18,000 36,000
36,000 72,000
125,000 250,000
DS785UM1