Cirrus Logic EP93 Series User Manual page 631

FISR
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15 14 13 12
Address:
0x808B_0180 - Read/Write
Default:
0x0000_0000
Definition:
FIR Status Register.
Bit Descriptions:
RSVD:
RFL:
RIL:
RFC:
DS785UM1
27 26 25 24
RSVD
11 10 9 8
RSVD
Reserved. Unknown During Read.
Receive Frame Lost. Set to a "1" when a ROR occurred at
the start of a new frame, before any data for the frame
could be put into the receive FIFO. This bit is cleared by
writing a "1" to this bit. This occurs if the last entry in the
FIFO already contains a valid EOF bit from a previous
frame when a FIFO overrun occurs. The ROR bit cannot
be placed into the FIFO and all data associated with the
frame is lost.
Receive Information Buffer Lost. Set to a "1" when the last
data for a frame is read from the receive FIFO (via the
IrData register) and the RFC bit is still set from a previous
end of frame. It indicates that data in the IrRIB register for
the previous frame was lost. This can occur if the CPU
does not respond to the RFC interrupt before another
frame completes and is read from the IrData register by
the DMA controller. This bit is cleared by writing a "1" to
this bit.
Received Frame Complete. Set to "1" when the last data
for a frame is read from the receive FIFO (via the IrData
register). This event also triggers the IrRIB to load the
IrFlag and byte count. This bit is cleared when the IrRIB
register is read.
Copyright 2007 Cirrus Logic
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7 6 5 4
RFL RIL RFC
IrDA
EP93xx User's Guide
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3 2 1 0
RFS TAB TFC TFS
17-35
17