Cirrus Logic EP93 Series User Manual page 10

EP93xx User's Guide
14.2.1.9 Interrupt Generation Logic .........................................................................14-4
14.2.1.10 Synchronizing Registers and Logic .........................................................14-5
14.2.2 UART Operation ..........................................................................................................14-5
14.2.2.1 Error Bits....................................................................................................14-6
14.2.2.2 Disabling the FIFOs ...................................................................................14-6
14.2.2.3 System/diagnostic Loopback Testing ........................................................14-6
14.2.2.4 UART Character Frame.............................................................................14-6
14.2.3 Interrupts .....................................................................................................................14-7
14.2.3.1 UARTMSINTR ...........................................................................................14-7
14.2.3.2 UARTRXINTR............................................................................................14-7
14.2.3.3 UARTTXINTR ............................................................................................14-7
14.2.3.4 UARTRTINTR............................................................................................14-8
14.2.3.5 UARTINTR.................................................................................................14-8
14.3 Modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8
14.4 HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-8
14.4.1 Overview of HDLC Modes ...........................................................................................14-9
14.4.2 Selecting HDLC Modes ...............................................................................................14-9
14.4.3 HDLC Transmit..........................................................................................................14-11
14.4.4 HDLC Receive...........................................................................................................14-11
14.4.5 CRCs .........................................................................................................................14-12
14.4.6 Address Matching......................................................................................................14-12
14.4.7 Aborts ........................................................................................................................14-13
14.4.8 DMA...........................................................................................................................14-14
14.4.9 Writing Configuration Registers.................................................................................14-14
14.5 UART1 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-14
14.5.1 Clocking Requirements .............................................................................................14-15
14.5.2 Bus Bandwidth Requirements ...................................................................................14-16
14.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-17
Chapter 15. UART2 .............................................................................................. 15-1
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
15.2 IrDA SIR Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1
15.2.1 IrDA SIR Encoder/decoder Functional Description .....................................................15-1
15.2.1.1 IrDA SIR Transmit Encoder .......................................................................15-2
15.2.1.2 IrDA SIR Receive Decoder ........................................................................15-2
15.2.2 IrDA SIR Operation......................................................................................................15-3
15.2.2.1 System/diagnostic Loopback Testing ........................................................15-4
15.2.3 IrDA Data Modulation ..................................................................................................15-4
15.2.4 Enabling Infrared (Ir) Modes........................................................................................15-5
15.3 UART2 Package Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-5
15.3.1 Clocking Requirements ...............................................................................................15-5
15.3.2 Bus Bandwidth Requirements .....................................................................................15-6
15.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-7
Chapter 16. UART3 With HDLC Encoder........................................................... 16-1
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
16.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-1
16.2.1 UART3 Package Dependency.....................................................................................16-1
16.2.2 Clocking Requirements ...............................................................................................16-2
16.2.3 Bus Bandwidth Requirements .....................................................................................16-2
16.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16-3
x
©
Copyright 2007 Cirrus Logic, Inc. DS785UM1