Bpp Word Layout; Table 8-15. 8 Bpp Memory Layout For Source Image; Table 8-16. 8 Bpp Memory Layout For Destination Image; Table 8-17. 16 Bpp Memory Layout For Source Image - Cirrus Logic EP93 Series User Manual

8.5.2.2 8 BPP Word Layout

For a Block Copy where 4 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
starts at bit 24, etc. The start pixel, P2, is in the word at address 0x0000 and has a beginning
bit position of 16. This makes 16 = 0x10 the value that is used for the SPEL field in the
"SRCPIXELSTRT"
Address 31
0x0000
0x0004
Let the starting SDRAM address of the destination image be 0x0030.
Pixel 2 starts at bit 16, Pixel 3 starts at bit 34, etc. The start pixel, P2, is in the word at address
0x0030 and has a beginning bit position of 16. This makes 16 = 0x10 the value that is used
for the SPEL field in the
The end pixel, P5, is in the word at address 0x0034 and has a beginning bit position of 8. This
makes 8 = 0x8 the value that is used for the EPEL field in the
Note:The word count for this example would be: 2 - 1 = 1 words, since P5 ends in the 2nd word.
So, WIDTH = 0x1 would be written to the
Address 31
0x0030
0x0034
8.5.2.3 16 BPP WORD Layout
For a Block Copy where 8 pixels are transferred per scan line, let the starting SDRAM
address of the source image be 0x0000.
starts at bit 16, etc. The start pixel, P0, is in the word at address 0x0000 and has a beginning
bit position of 0. This makes 0 = 0x0 the value that is used for the SPEL field in the
"SRCPIXELSTRT"
Address 31
0x0000
0x0004
0x0008
0x000C
DS785UM1
Table 8-15
register.

Table 8-15. 8 BPP Memory Layout for Source Image

24 23
P3 P2
P7 P6
"DESTPIXELSTRT"

Table 8-16. 8 BPP Memory Layout for Destination Image

24 23
P3 P2
P7 P6
Table 8-17
register.

Table 8-17. 16 BPP Memory Layout for Source Image

P1
P3
P5
P7
Copyright 2007 Cirrus Logic
shows that Pixel 2 starts at bit 16, Pixel 3
16 15 8 7
P1
P5
register.
"DESTPIXELSTRT"
"BLKDESTWIDTH" register.
16 15 8 7
P1
P5
shows that Pixel 0 starts at bit 0, Pixel 1
16 15
P0
P2
P4
P6
Graphics Accelerator
EP93xx User's Guide
0
P0
P4
Table 8-16 shows that
register.
0
P0
P4
0
8-11
8