Cirrus Logic EP93 Series User Manual page 546

UART1 With HDLC and Modem Control Signals
EP93xx User's Guide
UART1IntIDIntClr
31 30
14
15 14
Address:
Default:
Definition:
Bit Descriptions:
14-24
CTS:
29 28 27 26
13 12 11 10
RSVD
0x808C_001C - Read/Write
0x0000_0000
UART Interrupt Identification and Interrupt Clear Register.
RSVD:
RTIS:
TIS:
RIS:
MIS:
Copyright 2007 Cirrus Logic
Clear To Send status. This bit is the complement of the
UART clear to send (nUARTCTS) modem status input.
That is, the bit is 1 when the modem status input is 0.
25 24 23 22
RSVD
9 8 7 6
Reserved. Unknown During Read.
Receive Timeout Interrupt Status. This bit is set to 1 if the
UARTRTINTR receive timeout interrupt is asserted. This
bit is cleared when the receive FIFO is empty or the
receive line goes active.
Transmit Interrupt Status.
1 - The UARTTXINTR transmit interrupt is asserted, which
occurs when the transmit FIFO is not full.
0 - The transmit FIFO is full.
Receive Interrupt Status.
1 - The UARTRXINTR receive interrupt is asserted, which
occurs when the receive FIFO is not empty.
0 - The receive FIFO is empty.
Modem Interrupt Status. This bit is set to 1 if the
UARTMSINTR modem status interrupt is asserted. This
bit is cleared by writing any value to this register.
21 20 19 18
5 4 3 2
RTIS TIS
17 16
1 0
RIS MIS
DS785UM1