Setting The Video Memory Parameters - Cirrus Logic EP93 Series User Manual

7.4.10.1 Setting the Video Memory Parameters

The Raster Engine uses SDRAM for video frame buffers. The SDRAM locations for the video
frame buffers are defined by four registers:
"VLineStep" .
7.4.10.1.1 Setting up the VidScrnPage Register
The VidScrnPage
beginning of SDRAM memory space. With the combination of SDSEL in
it forms the absolute address for the starting location of the video memory. It is possible to
provide for a panning feature by altering the address of the start location at run time. This
address also represents the 0,0 pixel position, which is in the upper left corner of the video
image.
7.4.10.1.2 Setting up the ScrnLines Register
The "ScrnLines"
LineLength size that are to be fetched and forwarded to the FIFO. The 'number of lines' must
be programmed to be one less than the desired number of lines, because a programmed
value of 0x0 specifies a single line. The maximum value is 0x7FF for 2048 lines.
7.4.10.1.3 Setting up the LineLength Register
The "LineLength"
fetch from SDRAM for each scan line. This value is always one less than the needed number
of 32-bit words because a programmed value of 0x0 specifies a single 32-bit word.
For example, a display width of eighty 8-bit pixels requires that twenty 32-bit words be
fetched from the SDRAM video frame buffer for each scan line, since four 8-bit pixels can be
packed into a single 32-bit word (80/4=20).
7.4.10.1.4 Setting up the VLineStep Register
At the end of fetching LineLength of data for the first scan line, the Raster Engine will take the
value in the "VLineStep"
determine the starting SDRAM address for the next scan line. Generally, this value is the
same as LineLength + 0x1. However, it is possible to have an image in SDRAM that is larger
then the current display. This larger image can be cropped by the proper programming of
"VidScrnPage" ,
7.4.10.1.5 Memory Setup Example
Assume that a video display is 640 x 480 with a color depth of 4 bpp and that the start of
video memory (display pixel coordinate 0,0) is the address determined by SDSEL + 0x1000.
The register settings for this example are:
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
register provides the starting address for the video memory relative to the
register is used by the Raster Engine to specify the number of lines of
register contains the number of 32-bit words that the Raster Engine must
register and add it to the base address
"VLineStep" , and "ScrnLines"
VidScrnPage = 0x1000 (assume SDSEL = 0)
ScrnLines = 480 - 1 = 479 = 0x1DF
LineLength = (640 x 4bpp / 32) - 1 = 79 = 0x4F
Copyright 2007 Cirrus Logic
"VidScrnPage" , "ScrnLines"
("VidScrnPage"
registers.
EP93xx User's Guide
, "LineLength" , and
VideoAttribs register,
) to
7-31
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