Cirrus Logic EP93 Series User Manual page 573

Default:
0x0000_0000
Definition:
UART Interrupt Identification and Interrupt Clear Register. Interrupt status is
read from UART2IntIDIntClr. A write to UART2IntIDIntClr clears the modem
status interrupt. All the bits are cleared to 0 when reset.
Bit Descriptions:
RSVD:
RTIS:
TIS:
RIS:
MIS:
UART2IrLowPwrCntr
31 30 29 28
15 14 13 12
Address:
0x808D_0020 - Read/Write
Default:
0x0000_0000
Definition:
UART IrDA Low Power Divisor Register. This is an 8-bit read/write register
that stores the low-power counter divisor value used to generate the
IrLPBaud16 signal by dividing down of UARTCLK. All the bits are cleared to 0
when reset.
Bit Descriptions:
RSVD:
DS785UM1
Reserved. Unknown During Read.
Receive Timeout Interrupt Status. This bit is set to "1" if the
receive timeout interrupt is asserted.
Transmit Interrupt Status. This bit is set to "1" if the
transmit interrupt is asserted.
Receive Interrupt Status. This bit is set to "1" if the receive
interrupt is asserted.
Modem Interrupt Status. This bit is set to "1" if the modem
status interrupt is asserted.
27 26 25
11 10 9
RSVD
Reserved. Unknown During Read.
Copyright 2007 Cirrus Logic
24 23 22 21
RSVD
8 7 6 5
UART2
EP93xx User's Guide
20 19 18 17
4 3 2 1
ILPDV
15
16
0
15-15