Cirrus Logic EP93 Series User Manual page 593

UART3HDLCRXInfoBuf
31 30 29 28
15 14 13 12
RSVD
Address:
0x808E_0218 - Read/Write
Default:
0x0000_0000
Definition:
HDLC Receive Information Buffer Register. This register is loaded when the
last data byte in a received frame is read from the receive FIFO. The CPU has
until the end of the next frame to read this register, or the RIL bit in the HDLC
Status Register will be set.
Bit Descriptions:
RSVD:
BC:
BFRE:
BROR:
BCRE:
BRAB:
DS785UM1
27 26 25 24
RSVD
11 10 9 8
BC
Reserved. Unknown During Read.
Received frame Byte Count.
The total number of valid bytes read from the RX FIFO
during the last HDLC frame.
Buffered Framing Error.
0 - No framing errors were encountered in the last frame.
1 - A framing error occurred during the last frame, causing
the remainder of the frame to be discarded.
Buffered Receiver Over Run.
0 - The RX buffer did not overrun during the last frame.
1 - The receive FIFO did overrun during the last frame.
The remainder of the frame was discarded.
Buffered CRC Error.
0 - No CRC check errors occurred in the last frame.
1 - The CRC calculated on the incoming data did not
match the CRC value contained in the last frame.
Buffered Receiver Abort.
0 - No abort occurred in the last frame.
1 - The last frame was aborted.
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
23 22 21 20
7 6 5 4
EP93xx User's Guide
19 18 17 16
3 2 1 0
BFRE BROR BCRE BRAB
16-17
16