Cirrus Logic EP93 Series User Manual page 231

LineCarry
31 30 29 28
15 14 13 12
RSVD
Address: 0x8003_003C
Default: 0x0000_0000
Definition: Horizontal Line Carry Value register
Bit Descriptions:
RSVD:
LCARY:
EOLOffset
31 30 29 28
15 14 13 12
Address: 0x8003_0230
Default: 0x0000_0000
Definition: End-of-line Offset Register.
Bit Descriptions:
RSVD:
OFFSET:
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
27 26 25 24
RSVD
11 10 9 8
Reserved - Unknown during read
Line Carry - Read/Write
When the Horizontal down counter counts down to the
written LCARY value, a carry is sent to increment the
Vertical counter. This provides for timing skew between
the vertical and horizontal video signals. Please refer to
the video signalling timing diagrams in
Figure 7-10.
27 26 25 24
RSVD
11 10 9 8
OFFSET
Reserved - Unknown during read
Offset - Read/Write
The Offset value written to this field is added to the
address at the end of every other video line if the Offset
value is not 0x0. This allows splitting the left and right
halves of the display.
Copyright 2007 Cirrus Logic
23 22 21 20
7 6 5 4
LCARY
23 22 21 20
7 6 5 4
EP93xx User's Guide
19 18 17 16
3 2 1 0
Figure 7-9 and
19 18 17 16
3 2 1 0
7-49
7