Cirrus Logic EP93 Series User Manual page 557

RFS:
TAB:
TFC:
TFS:
DS785UM1
UART1 With HDLC and Modem Control Signals
Receive FIFO Service request. (Read Only)
This bit is a copy of the RIS bit in the UART interrupt
identification register.
0 - RX FIFO is empty or RX is disabled.
1 - RX FIFO not empty and RX enabled.
May generate an interrupt and signal a DMA service
request.
Transmitted Frame Aborted. (Read/Write)
Set "1" when a transmitted frame is terminated with an
abort. Cleared by writing to a "1" to this bit.
Transmit Frame Complete. (Read/Write)
Set to "1" whenever a transmitted frame completes,
whether terminated normally or aborted. Cleared by
writing to a "1" to this bit.
Transmit FIFO Service request. (Read Only)
This bit is a copy of the TIS bit in the UART interrupt
identification register.
0 - TX FIFO is full or TX disabled.
1 - TX FIFO not full and TX enabled. May generate an
interrupt and signal a DMA service request.
Copyright 2007 Cirrus Logic
EP93xx User's Guide
14
14-35