Cirrus Logic EP93 Series User Manual page 568

UART2
EP93xx User's Guide
15
UART2LinCtrlMid
31 30
15 14
Address:
Default:
15-10
FEN:
STP2:
EPS:
PEN:
BRK:
29 28 27 26
13 12 11 10
RSVD
0x808D_000C - Read/Write
0x0000_0000
Copyright 2007 Cirrus Logic
FIFO Enable.
1 - Transmit and receive FIFO buffers are enabled (FIFO
mode).
0 - The FIFOs are disabled (character mode). (That is, the
FIFOs become 1-byte-deep holding registers.)
Two Stop Bits Select.
1 - Two stop bits are transmitted at the end of the frame.
0 - One stop bit is transmitted at the end of the frame.
The receive logic does not check for two stop bits being
received.
Even Parity Select.
1 - Even parity generation and checking is performed
during transmission and reception (this checks for an even
number of "1"s in data and parity bits).
0 - Odd parity is performed (this checks for an odd number
of "1"s).
This bit has no effect when parity is disabled by Parity
Enable (bit 1) being cleared to 0.
Parity Enable.
1 - Parity checking and generation is enabled,
0 - Parity checking is disabled and no parity bit added to
the data frame.
Send Break.
1 - A low level is continually output on the UARTTXD
output, after completing transmission of the current
character. This bit must be asserted for at least one
complete frame transmission time in order to generate a
break condition. The transmit FIFO contents remain
unaffected during a break condition.
0 - For normal use, this bit must be cleared.
25 24 23 22
RSVD
9 8 7 6
21 20 19 18
5 4 3 2
BR
17 16
1 0
DS785UM1