Cirrus Logic EP93 Series User Manual page 679

RXDIR:
I2SRXCtrl
31 30 29 28
15 14 13 12
Address:
0x8082_005C - Read/Write
Default:
0x0000_0000
Definition:
Control Register
Bit Descriptions:
RSVD:
ROFLIE:
RXFull_int_level: Rx full interrupt level select.
I2SRXWrdLen
31 30 29 28
15 14 13 12
Address:
0x8082_0060 - Read/Write
Default:
0x0000_0000
Definition:
Word Length
DS785UM1
Receive data shift direction.
0 - MSB first
1 - LSB first
27 26 25 24 23
11 10 9 8 7
RSVD
Reserved. Unknown During Read. Must be written as "0".
Receive interrupt enable.
Active high
0 - Generate interrupt when FIFO is half full.
1 - Generate interrupt when FIFO is full.
27 26 25 24
11 10 9 8
RSVD
Copyright 2007 Cirrus Logic
22 21 20
RSVD
6 5 4
23 22 21
RSVD
7 6 5
2
I S Controller
EP93xx User's Guide
19 18 17 16
3 2 1
ROFLIE RXFull_int_level
20 19 18 17
4 3 2 1
WL
21
0
16
0
21-23