Cirrus Logic EP93 Series User Manual page 392

1/10/100 Mbps Ethernet LAN Controller
EP93xx User's Guide
9
TXDThrshld
31 30
15 14
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
9-90
RDST:
29 28 27 26
RSVD
13 12 11 10
RSVD
0x8001_00E4 - Read/Write
0x0004_0002
0x0000_0000
Unchanged
Transmit Descriptor Threshold register. The transmit descriptor thresholds are
used to set a limit on the amount of empty space allowed in the MAC's
transmit descriptor FIFO before a bus request will be scheduled. When the
number of empty words in the FIFO exceeds the threshold value, the
Descriptor Processor will schedule a bus request to transfer descriptors. The
actual posting of the bus request may be delayed due to lack of resources in
the MAC, such as a TXDEnq equal to zero. The lower two bits of the
thresholds are always zero.
RSVD:
0:
TDHT:
Copyright 2007 Cirrus Logic
Receive Descriptor Soft Threshold.
The hard and soft threshold work in exactly the same
manner except one. The soft threshold will not cause a
bus request to be made if the bus is currently in use, but
only when it is deemed to be idle (no transfers for four
AHB clocks). The hard threshold takes effect immediately
regardless of the state of the bus. This operation allows for
more efficient use of the AHB bus by allowing smaller
transfers to take place when the bus is lightly loaded and
requesting larger transfers only when the bus is more
heavily loaded.
25 24 23 22
9 8 7 6
Reserved. Unknown During Read.
Must be written as "0".
Transmit Descriptor Hard Threshold.
21 20 19 18
TDHT
5 4 3 2
TDST
17 16
0 0
1 0
0 0
DS785UM1