Cirrus Logic EP93 Series User Manual page 594

UART3 With HDLC Encoder
EP93xx User's Guide
UART3HDLCSts
31 30
15 14
16
RSVD CRE
Address:
Default:
Definition:
Bit Descriptions:
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
16-18
29 28 27 26
13 12 11 10
ROR TBY RIF RSVD
0x808E_021C - Read/Write
0x0000_0000
HDLC Status Register. The TFS and RFS bits in this register are replicas of
bits in the UART3 status register.
RSVD:
CRE:
changes with reads from the RX FIFO.
ROR:
changes with reads from the RX FIFO.
TBY:
RIF:
25 24 23 22
RSVD
9 8 7 6
RAB RTO EOF RFL
Reserved. Unknown During Read.
CRC Error. (Read Only)
0 - No CRC check errors encountered in incoming frame.
1 - CRC calculated on the incoming data does not match
CRC value contained within the received frame. This bit is
set with the last data in the incoming frame along with
EOF.
Receive FIFO Overrun. (Read Only)
0 - RX FIFO has not overrun.
1 - RX logic attempted to place data in the RX FIFO while
it was full. The most recently read data is the last valid
data before the overrun. The rest of the incoming frame is
dropped. EOF is also set.
Transmitter Busy. (Read Only)
0 - TX is idle, disabled, or transmitting an abort.
1 - TX is currently sending a frame (address, control, data,
CRC or start/stop flag).
Receiver In Frame. (Read Only)
0 - RX is idle, disabled or receiving start flags
1 - RX is receiving a frame.
Copyright 2007 Cirrus Logic
21 20 19 18
5 4 3 2
RIL RFC RFS TAB
17 16
1 0
TFC TFS
DS785UM1