Cirrus Logic EP93 Series User Manual page 230

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
7
VLineStep
31 30
15 14
RSVD
Address: 0x8003_0038
Default: 0x0000_0000
Definition: Video Line Step Size Register
Bit Descriptions:
7-48
LEN:
29 28 27 26
13 12 11 10
RSVD:
STEP:
Copyright 2007 Cirrus Logic
Length - Read/Write
The Length value written to this field specifies, in 32-bit
words, the length of video lines that are scanned to the
display. Please see "Setting up the LineLength Register"
on page 7-31 and "Memory Setup Example" on page
The remainder of the last word in a video line may not be
used as long as the blanking time is greater than the
remaining number of pixels. The extra pixels will enter the
video chain, but will exit the pipeline during the blanking
interval. When the end of LEN is reached, STEP in the
VLineStep register is added to the address for video data.
25 24 23 22
RSVD
9 8 7 6
STEP
Reserved - Unknown during read
Step - Read/Write
When the end of the video line is reached (see LEN in
LineLength register), the Step value written to this field
(specified in 32-bit words) is added to the address for
every video line that is scanned to the display. Please see
"Memory Setup Example" on page
This allows the screen width to be smaller than the video
image width in SDRAM.
21 20 19 18
5 4 3 2
7-31.
7-31.
17 16
1 0
DS785UM1