Cirrus Logic EP93 Series User Manual page 260

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User's Guide
Bit Descriptions:
7
VidSigCtrl
31 30
EN RSVD SPCLK
15 14
Address: 0x8003_0204
Default: 0x0000_0000
Definition: Video Output Signature Control register
Bit Descriptions:
7-78
RSVD:
SIGVAL:
29 28 27 26
BRIGHT CLKEN BLANK
13 12 11 10
EN:
RSVD:
SPCLK:
BRIGHT:
Copyright 2007 Cirrus Logic
Reserved - Unknown during read
Signature Results Value - Read ONly
The Signature Results Value contained in this field is the
16-bit result of the video output signature calculation. This
Signature Results Value is usually updated once per frame
based on the SigClrStr
operation, the Signature Results Value is updated once
every 12 frames.
25 24 23 22
HSYNC VSYNC
9 8 7 6
PEN
Enable - Read/Write
Writing a '1' to this bit enables the Linear Feedback Shift
Register (LFSR).
Writing a '0' to this bit disables the LFSR.
Reserved - Unknown during read
Smart Panel/Pixel Clock - Read/Write
Writing a '1' to this bit enables the SPCLK output for
calculation in the video signature.
Writing a '0' to this bit disables the SPCLK output for
calculation in the video signature.
Bright - Read/Write
Writing a '1' to this bit enables the Brightness control
output for calculation in the video signature.
Writing a '0' to this bit disables the Brightness control
output for calculation in the video signature.
location. During grayscale
21 20 19 18
PEN
5 4 3 2
17 16
1 0
DS785UM1