Cirrus Logic EP93 Series User Manual page 420

DMA Controller
EP93xx User's Guide
STATUS
31 30
15 14
10
RSVD
Address:
Definition:
Bit Descriptions:
10-26
29 28 27 26
13 12 11 10
BYTES
Channel Base Address + 0x000C - Read Only
This is the channel status register, which is a read-only register, used to
provide status information with respect to the DMA channel.
RSVD:
Stall:
NFB:
ChError:
BYTES:
Copyright 2007 Cirrus Logic
25 24 23 22
RSVD
9 8 7 6
NextBuffer
Reserved. Unknown During Read.
A "1" indicates channel is stalled and cannot currently
transfer data because a base address has not been
programmed. When the channel is first enabled, the Stall
bit is suppressed until the first buffer has been transferred,
that is, no stall interrupt generated when STALL state
entered from IDLE state, only when entered from ON
State. The STALL state can be cleared by writing a base
address or disabling the DMA channel. The reason for
channel completion can be ascertained by reading the
BYTES_REMAINING register, if it is zero, the channel was
stopped by the DMA Channel; if it is non-zero, the
peripheral ended transfer with TxEnd/RxEnd. If the
transfer ended with error, ChError bit/interrupt is set.
A "1" indicates the Channel FSM has moved from NEXT
State to ON State. This means that the channel is currently
transferring data from a DMA buffer but the next base
address for the next buffer in the transfer has not been
programmed, and may now be.
0 - Not in ON State, not ready for next buffer update.
1 - In ON State, ready for next buffer BASE/MAXCOUNT
updates. NFB interrupt generated if not masked.
Indicates error status of buffer transfer:
0 - The last buffer transfer completed without error.
1 - The last buffer transfer terminated with an error.
This is the number of valid DMA data currently stored by
the channel in the DMA Controller in packer or unpacker.
Usually used for test/debug.
21 20 19 18
5 4 3 2
Current State ChError RSVD
17 16
1 0
NFB STALL
DS785UM1