Cirrus Logic EP93 Series User Manual page 440

DMA Controller
EP93xx User's Guide
Definition:
Bit Descriptions:
10
10-46
DMA Channel Arbitration Register. This bit controls the DMA channel
arbitration.
RSVD: Reserved. Unknown During Read.
CHARB: This bit controls DMA channel arbitration. It is reset to "0",
thus giving a default setting of internal Memory-to-
Peripheral channels having a higher priority than Memory-
to-Memory channels. This bit can be set to "1" to reverse
the default order, that is, giving M2M transfers a higher
priority than internal M2P.
Copyright 2007 Cirrus Logic
DS785UM1