Cirrus Logic EP93 Series User Manual page 221

STRT:
VActiveStrtStop
31 30 29 28
RSVD
15 14 13 12
RSVD
Address: 0x8003_0008
Default: 0x0000_0000
Definition: Vertical Active Start/Stop register
Bit Descriptions:
RSVD:
STOP:
STRT:
DS785UM1
Raster Engine With Analog/LCD Integrated Timing and Interface
When the Vertical counter counts down to the written
STOP value, the VSYNC signal on the V_CSYNC pin will
go inactive if CSYNC = '0' and SYNCEN = '1' in the
VideoAttribs
timing diagrams shown in
Start - Read/Write
When the Vertical counter counts down to the written
STRT value, the VSYNC signal on the V_CSYNC pin will
go active if CSYNC = '0' and SYNCEN = '1' in the
VideoAttribs
27 26 25 24
11 10 9 8
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VACTIVE signal becomes inactive (stops).
This indicates the end of the active video portion for the
Vertical frame. Please refer to the video signalling timing
diagrams in
internal block signal. The active video interval is controlled
by the logical OR of VACTIVE and HACTIVE.
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VACTIVE signal becomes active (starts). This
indicates the start of the active video portion for the
Vertical frame. Please refer to the video signalling timing
diagrams in
internal block signal. The active video interval is controlled
by the logical OR of VACTIVE and HACTIVE.
Copyright 2007 Cirrus Logic
register. Please refer to the video signalling
Figure 7-9
register.
23 22 21 20
STOP
7 6 5 4
STRT
Figure 7-9 and Figure
Figure 7-9 and Figure
EP93xx User's Guide
and Figure 7-10.
19 18 17 16
3 2 1 0
7-10. VACTIVE is an
7-10. VACTIVE is an
7-39
7