Cirrus Logic EP93 Series User Manual page 369

Soft Reset:
0x0000_0000
Definition:
MII Status Register
Bit Descriptions:
RSVD:
Busy:
Descriptor Processor Registers
The Descriptor Processor Registers are in three parts: the bus master control, receive
registers, and transmit registers.
BMCtl
31 30 29 28
15 14 13 12
RSVD MT TT
Address:
0x8001_0080 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Bus Master Control Register
Bit Descriptions:
RSVD:
DS785UM1
Reserved. Unknown During Read.
MII Busy. The Busy bit is set whenever a command is
written to the MII Command Register. It is cleared when
the operation has been completed.
27 26 25 24
RSVD
11 10 9 8
UnH TxChR TxDis TxEn
Reserved. Unknown During Read.
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
23 22 21 20
7 6 5 4
RSVD EH2 EH1 EEOB
EP93xx User's Guide
19 18 17 16
3 2 1 0
RSVD RxChR RxDis RxEn
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